AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 141

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Am79C940 MACE Rev C0 Silicon
Errata
The items below are the known errata for Rev C0 silicon. Rev C0 is the production silicon.
The enclosed is a list of known errata’s encountered with the MACE Rev C0 device. Each of these errata’s is pro-
vided with description, implication, and workaround (if possible). Where the errata was published in a previous er-
rata list, is so noted. Other than those listed exceptions below that have not been fixed, the MACE Rev C0
production device is fully functional.
The "Description" section of the errata gives a brief description of the problem. The "Implication" section of the
errata describes the effects of the problem in a system configuration. The "Workaround" section of the errata de-
scribes methods to minimize the system effects. The “Status” section of the errata describes when and how the
problem will be corrected.
Current package marking for this revision: Line 1: <Logo>
Value of CHIPID register for this revision: CHIPID[15:00] = 3940h
1) Receive Fragment Frame Treated as a New Packet Even After Receive FIFO Overflows:
2) In Low Latency Receive Mode, Loses Synchronization When Connected to a Coaxial Transceiver via the
AUI Port:
Description: The MACE device continues to receive the remains of a long packet even after the receive FIFO
overflows. If this data stream has the ’Start of Frame’ (SFD) bit pattern "10101011" (and no "00" bit pattern
before the "SFD" pattern) and the destination address field of the packet matches the station address after
the SFD bit pattern, or if the MACE device is in promiscuous mode, the remaining portion of the long packet
will be received and treated by the MACE device as a new packet even though the receive status will show
an FCS error.
Implication: There is no impact of any kind if the receive FIFO overflow is not permitted by the system design.
The likelihood of such an occurrence of the above conditions is extremely remote. Should this condition occur,
this will impact performance only in products using the “cut-through” method. This is because the "cut-
through" method will not look at the FCS field, which would indicate an error in the packet received.
Workaround: Check for FCS error after the packet is received.
Status: No current plan to fix this item.
Description: In low latency receive mode, the MACE device loses synchronization when connected to a co-
axial (10BASE2) transceiver. The problem occurs when connecting the MACE to a coaxial transceiver via the
AUI interface, and at the same time the MACE device is programmed into low latency receive mode. When
a collision occurs in the media and if MACE device continues to receive data, after the collision is ended, the
MACE device loses synchronization.
Implication: No performance impact to the MACE device if the 10BASE-T port is used instead of a 10BASE2
coaxial transceiver connected to the AUI port of the MACE device.
Workaround: This condition is being validated at this time. In the meantime, it is recommended that if the
product is to be used in a network topology where a 10BASE2 coaxial transceiver is connected to the AUI
port, care must be exercised to avoid using the MACE device in low latency receiver mode.
APPENDIX C
Line 2: Am79C940BKC (Assuming package is PQFP)
Line 3: <Date Code>
Line 4: (c) 1992 AMD
Am79C940
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