AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 69

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

Bit 0
Chip Identification Register
(CHIPID [15-00])
This 16-bit value corresponds to the specific version of
the MACE device being used. The value will be
programmed to X940h, where X is a value dependent
on version. [For the current version of the MACE de-
vice, X = 3 to denote Rev C0 silicon.]
Internal Address
Configuration (IAC)
This register allows access to and from the multi-byte
Physical Address and Logical Address Filter locations,
using only a single byte location.
The MACE device will reset the IAC register PHYADDR
and LOGADDR bits after the appropriate number of
read or write cycles have been executed on the Physical
Address Register or the Logical Address Filter. Once the
LOGADDR bit is set, the MACE device will reset the bit
after 8 read or write operations have been performed.
Once the PHYADDR bit is set, the MACE device will
reset the bit after 6 read or write operations have been
performed. The MACE device makes no distinction be-
tween read or write operations, advancing the internal
address RAM pointer with each access. If both PHY-
ADDR and LOGADDR bits are set, the MACE device
will accept only the LOGADDR bit. If the PHYADDR bit
is set and the Logical Address Filter location is ac-
cessed, a DTV will not be returned. Similarly, if the
LOGADDR bit is set and the Physical Address Register
location is accessed, DTV will not be returned. PHY-
CHIPID [07–00]
CHIPID [15–08]
AWAKE
continue to operate even during
SLEEP. Incoming packet activity
will be passed to the EADI port
pins permitting detection of spe-
cific frame contents used to ini-
tiate
RWAKE must be programmed
prior to SLEEP being asserted
for this function to operate.
RWAKE is not cleared by
SLEEP, only by activation of the
SWRST bit or RESET pin.
Auto Wake. When set prior to
the SLEEP pin being activated,
the 10BASE-T receiver section
will continue to operate even
during SLEEP, and will activate
the LNKST pin if Link Pass is
detected. AWAKE must be pro-
grammed prior to SLEEP being
asserted for this function to
operate. AWAKE is not cleared
by SLEEP, only by activation of
the SWRST bit or RESET pin.
a
(REG ADDR 18)
(REG ADDR 16 &17)
wake-up
sequence.
Am79C940
ADDR or LOGADDR can be set in the same cycle as
ADDRCHG.
Bit
Bit 7
Bit 6-3
Bit 2
Bit 1
Bit 0
Logical Address Filter
(LADRF [63–00])
This 64-bit mask is used to accept incoming Logical
Addresses. The Logical Address Filter is expected to
be programmed at initialization (after hardware or
ADDRCHG
LADRF [63–00]
ADDRCHG Address Change. When set,
RES
PHYADDR Physical Address Reset. When
LOGADDR Logical Address Reset. When
RES
RES
Name
RES
RES
Description
allows the physical and/or logi-
cal address to be read or pro-
grammed. When ADDRCHG is
set, ENRCV will be cleared, the
MPC will be stopped, and the
last or current in progress
receive frame will be received as
normal. After the frame com-
pletes, access to the internal
address RAM will be permitted,
indicated by the MACE device
clearing the ADDRCHG bit.
Please refer to the register
description of the ENRCV bit in
the MAC Configuration Control
register (REG ADDR 13) for the
effect of clearing the ENRCV bit.
Normal
resumed once the physical/logi-
cal address has been changed,
by setting ENRCV.
Reserved. Read as zeroes.
Always write as zeroes.
set, successive reads or writes
to the Physical Address Register
will occur in the order PADR
[07–00],
PADR [47–40]. Each read or
write operation on the PADR
location will auto-increment the
internal pointer to access the
next most significant byte.
set, successive reads or writes
to the Logical Address Filter will
occur in the order LADRF [07–
00], LADRF [15-08],....,LADRF
[63–56]. Each read or write
operation on the LADRF location
will auto-increment the internal
pointer to access the next most
significant byte.
Reserved. Read as zero. Always
write as zero.
RES
PHYADDR LOGADDR
reception
PADR
(REG ADDR 20)
[15–08],....,
can
RES
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be