AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 45

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

external encoder/decoder is responsible for asserting
the CLSN pin after each transmission. In DAI mode,
SEQ Test has no relevance.
Jabber Function
The Jabber function inhibits the twisted pair transmit
function of the MACE device if the TXD /TXP circuits
are active for an excessive period (20-150 ms). This
prevents any one node from disrupting the network due
to a stuck-on or faulty transmitter. If this maximum
transmit time is exceeded, the data path through the
10BASE-T transmitter circuitry is disabled (although
Link Test pulses will continue to be sent), the CLSN pin
is asserted, the Jabber bit (JAB in the Interrupt Regis-
ter) is set and the INTR pin will be asserted providing
the JABM bit (Interrupt Mask Register) is cl eared.
Once the internal transmit data stream from the MEN-
DEC stops (TXEN deasserts), an unjab time of
250-750 ms will elapse before the MACE device
deasserts the CLSN indication and re-enables the
transmit circuitry.
When jabber is detected, the MACE device will assert
the CLSN pin, de-assert the TXEN pin (regardless of
internal MENDEC activity), and allow the RXCRS pin to
indicate the current state of the RXD pair. If there is no
receive activity on RXD , only CLSN will be active dur-
ing jabber detect. If there is RXD activity, both CLSN
and RXCRS will be active.
External Address Detection Interface
(EADI)
This interface is provided to allow external perfect ad-
dress filtering. This feature is typically utilized for termi-
nal server, bridge and/or router type products. The use
of external logic is required, to capture the serial bit
stream from the MACE device, and compare this with
a table of stored addresses or identifiers. See the EADI
port diagram in the Systems Applications section,
Network Interfaces sub-section, for details.
The EADI interface operates directly from the NRZ
decoded data and clock recovered by the Manchester
decoder. This allows the external address detection to
be performed in parallel with frame reception and
address comparison in the MAC Station Address
Detection (SAD) block.
SRDCLK is provided to allow clocking of the receive bit
stream from the MACE device, into the external
address detection logic. Once a received packet com-
mences and data and clock are available from the
decoder, the EADI interface logic will monitor the alter-
nating (1,0) preamble pattern until the two ones of the
Start Frame Delimiter (1,0,1,0,1,0,1,1) are detected, at
which point the SF/BD output will be driven high.
After SF/BD is asserted the serial data from SRD
should be de-serialized and sent to a Content
Am79C940
Addressable Memory (CAM) or other address
detection device.
To allow simple serial to parallel conversion, SF/BD is
provided as a strobe and/or marker to indicate the
delineation of bytes, subsequent to the SFD. This fea-
ture provides a mechanism to allow not only capture
and/or decoding of the physical or logical (group)
address, but also facilitates the capture of header
information to determine protocol and or inter-network-
ing information. The EAM/R pin is driven by the exter-
nal address comparison logic, to either reject or accept
the packet. Two alternative modes are permitted, al-
lowing the external logic to either accept the packet
based on address match, or reject the packet if there is
no match. The two alternate methods are programmed
using the Match/Reject (M/
Control register.
If the M/R bit is set, the pin is configured as EAM
(External Address Match). The MACE device can be
configured with Physical, Logical or Broadcast Address
comparison operational. If an internal address match is
detected, the packet will be accepted regardless of the
condition of EAM. Additional addresses can be located
in the external address detection logic. If a match is
detected, EAM must go active within 600 ns of the last
bit in the destination address field (end of byte 6) being
presented on the SRD output, to guarantee frame
reception. In addition, EAM must go inactive after a
match has been detected on a previous packet, before
the next match can take place on any subsequent
packet. EAM must be asserted for a minimum pulse
width of 200 ns.
If the M/R bit is clear (default state after either the
RESET pin or SWRST bit have been activated), the pin
is configured as EAR (External Address Reject). The
MACE device can be configured with Physical, Logical
or Broadcast Address comparison operational. If an
internal address match is detected, the packet will be
accepted regardless of the condition of EAR. Incoming
packets which do not pass the internal address com-
parison will continue to be received by the MACE
device. EAR must be externally presented to the
MACE chip prior to the first assertion of RDTREQ, to
guarantee rejection of unwanted packets. This allows
approximately 58 byte times after the last destination
address bit is available to generate the EAR signal, as-
suming the MACE device is not configured to accept
runt packets. EAR will be ignored by the MACE device
from 64 byte times after the SFD, and the packet will be
accepted if EAR has not been asserted before this
time. If the MACE device is configured to accept runt
packets, the EAR signal must be generated prior to the
receive message completion, which could be as short
as 12 byte times (assuming six bytes for source
address, two bytes for length, no data, four bytes for
FCS) after the last bit of the destination address is
R
) bit in the Receive Frame
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