AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 39

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

* Requires trimming crystal spec; no trim is 50 ppm total
External Clock Drive Characteristics
When driving the oscillator from an external clock
source, XTAL2 must be left floating (unconnected). An
external clock having the following characteristics must
be used to ensure less than 0.5 ns jitter at DO .
MENDEC Transmit Path
The transmit section encodes separate clock and NRZ
data input signals into a standard Manchester encoded
serial bit stream. The transmit outputs (DO ) are
designed to operate into terminated transmission lines.
When operating into a 78 ohm terminated transmission
line, signaling meets the required output levels and
skew for Cheapernet, Ethernet and IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the SIA portion of the
MACE device. It is divided by two, to create the internal
transmit clock reference. Both clocks are fed into the
SIA’s Manchester Encoder to generate the transitions
in the encoded data stream. The internal transmit clock
is used by the SIA to internally synchronize the Internal
Transmit Data (ITXD) from the controller and Internal
Transmit Enable (ITENA). The internal transmit clock is
Parameter
1. Parallel Resonant Frequency
2. Resonant Frequency Error
3. Change in Resonant Frequency
pF)*
4. Crystal Capacitance
5. Motional Crystal Capacitance (C1)
6. Series Resistance
7. Shunt Capacitance
Clock Frequency:
Rise/Fall Time (tR/tF):
XTAL1 HIGH/LOW Time
XTAL1 Falling Edge to
Falling Edge Jitter:
(tHIGH/tLOW):
(CL = 20 pF)
With Respect To Temperature (CL = 20
20 MHz 0.01%
< 6 ns from 0.5 V
to V DD –0.5
40 – 60%
duty cycle
< 0.2 ns at
2.5 V input (V DD /2)
Min
–50
–40
Am79C940
also used as a stable bit rate clock by the receive
section of the SIA and controller.
The oscillator requires an external 0.005% crystal, or
an external 0.01% CMOS-level input as a reference.
The accuracy requirements if an external crystal is
used are tighter because allowance for the on-chip
oscillator must be made to deliver a final accuracy of
0.01%.
Transmission is enabled by the controller. As long as
the ITENA request remains active, the serial output of
the controller will be Manchester encoded and appear
at DO . When the internal request is dropped by the
controller, the differential transmit outputs go to one of
two idle states, dependent on TSEL in the Mode
Register (CSR15, bit 9):
Receive Path
The principal functions of the Receiver are to signal the
MACE device that there is information on the receive
pair, and separate the incoming Manchester encoded
data stream into clock and NRZ data.
The Receiver section (see Receiver Block Diagram)
consists of two parallel paths. The receive data path is
a zero threshold, wide bandwidth line receiver. The
carrier path is an offset threshold bandpass detecting
line receiver. Both receivers share common bias net-
works to allow operation over a wide input common
mode range.
TSEL HIGH:
TSEL LOW:
0.022
Nom
20
The idle state of DO yields “zero”
differential to operate transformer-
coupled loads.
In this idle state, DO+ is positive with
respect to DO– (logical\HIGH).
Max
+50
+40
20
35
7
Units
PPM
PPM
MHz
ohm
pF
pF
pF
39