AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 38

• Manufacturer Part Number: AM79C940JC/W
• Manufacturer: AMD [Advanced Micro Devices]

(ONE and MORE will be clear), and the transmit mes-
sage will be flushed from the XMTFIFO, either by reset-
ting the XMTFIFO (if no End-of-Frame tag exists) or by
moving the XMTFIFO read pointer to the next free lo-
cation (If an End-of-Frame tag is present). If retries
have been disabled by setting the DRTRY bit, the
MACE device will abandon transmission of the frame
on detection of the first collision. In this case, only the
RTRY bit will be set and the transmit message will be
flushed from the XMTFIFO. The RTRY condition will
cause the de-assertion of TDTREQ, and the assertion
of the INTR pin, providing the XMTINTM bit is cleared.
If a collision is detected after 512 bit times have been
transmitted, the collision is termed a late collision. The
MACE device will abort the transmission, append the
jam sequence and set the LCOL bit in the Transmit
Frame Status. No retry attempt will be scheduled on
detection of a late collision, and the XMTFIFO will be
flushed. The late collision condition will cause the
de-assertion of TDTREQ, and the assertion of the
INTR pin, providing the XMTINTM bit is cleared.
The IEEE 802.3 Standard requires use of a truncated
binary exponential backoff algorithm which provides a
controlled pseudo random mechanism to enforce the
collision backoff interval, before re-transmission is
attempted.
The MACE device implements a random number
g e n e r a t o r, c o n f i g u r e d t o e n s u r e t h a t n o d e s
experiencing a collision, will not have their retry inter-
vals track identically, causing retry errors.
The MACE device provides an alternative algorithm,
which suspends the counting of the slot time/IPG dur-
ing the time that receive carrier sense is detected. This
aids in networks where large numbers of nodes are
present, and numerous nodes can be in collision. It
effectively accelerates the increase in the backoff time
in busy networks, and allows nodes not involved in the
collision to access the channel whilst the colliding
nodes await a reduction in channel activity. Once chan-
38
See ANSI/IEEE Std 802.3-1990 Edition, 4.2.3.2.5:
“At the end of enforcing a collision (jamming),
the CSMA/CD sublayer delays before attempt-
ing to re-transmit the frame. The delay is an in-
teger multiple of slotTime. The number of slot
times to delay before the nth re-transmission
attempt is chosen as a uniformly distributed
random integer r in the range:
0
r
2 k , where k = min (n,10).“
Am79C940
nel activity is reduced, the nodes resolving the collision
time-out their slot time counters as normal.
If a receive message suffers a collision, it will be either
a runt, in which case it will be deleted in the Receive
FIFO, or it will be marked as a receive late collision,
using the CLSN bit in the Receive Frame Status regis-
ter. All frames which suffer a collision within the slot
time will be deleted in the Receive FIFO without
requesting host intervention, providing that the LLRCV
bit (Receive Frame Control) is not set. Runt packets
which suffer a collision will be aborted regardless of the
state of the RPA bit (User Test Register). If the collision
commences after the slot time, the MACE device
receiver will stop sending collided packet data to the
Receive FIFO and the packet data read by the system
will contain the amount of data received to the point of
collision; the CLSN bit in the Receive Frame Status
register will indicate the receive late collision. Note that
the Receive Message Byte Count will report the total
number of bytes during the receive activity, including
the collision.
In all normal receive collision cases, the MACE device
eliminates the transfer of packet data across the host
bus. In a receive late collision condition, the MACE chip
minimizes the amount transferred. These functions
preserve bus bandwidth utilization.
Manchester Encoder/Decoder (MENDEC)
The integrated Manchester Encoder/Decoder provides
the PLS (Physical Signaling) functions required for a
fully compliant IEEE 802.3 station. The MENDEC block
contains the AUI, DAI interfaces, and supports the
10BASE-T interface; all of which transfer data to appro-
priate transceiver devices in Manchester encoded for-
mat. The MENDEC provides the encoding function for
data to be transmitted on the network using the high
accuracy on-board oscillator, driven by either the crys-
tal oscillator or an external CMOS level compatible
clock generator. The MENDEC also provides the
decoding function from data received from the network.
The MENDEC contains a Power On Reset (POR)
circuit, which ensures that all analog portions of the
MACE device are forced into their correct state during
power up, and prevents erroneous data transmission
and/or reception during this time.
External Crystal Characteristics
When using a crystal to drive the oscillator, the follow-
ing crystal specification should be used to ensure less
than 0.5 ns jitter at DO