AM79C940JC/W AMD [Advanced Micro Devices], AM79C940JC/W Datasheet - Page 25
AM79C940JC/W
Manufacturer Part Number
AM79C940JC/W
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C940JCW.pdf
(144 pages)
- Current page: 25 of 144
- Download datasheet (2Mb)
Note:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
Notes:
1. PORTSEL [1–0] and ENPLSIO are located in the PLS Configuration Control register (REG ADDR 14).
2. This pin should be externally terminated, if unused, to reduce power consumption.
SLEEP
SLEEP
0
1
1
1
1
1
0
1
1
1
1
1
PORTSEL
PORTSEL
[1-0]
[1-0]
XX
XX
XX
XX
00
01
10
00
01
10
11
11
ENDPLSIO
ENDPLSIO
SRDCLK Configuration
X
X
1
1
1
1
0
1
1
1
1
0
SRD Configuration
Am79C940
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
Sleep Mode
AUI
10BASE-T
DAI Port
GPSI
Status Disabled
Interface Description
Interface Description
High Impedance
SRD Output
SRD Output
SRD Output
SRD Output
High Impedance
High Impedance
SRDCLK Output
SRDCLK Output
SRDCLK Output
SRDCLK Output
High Impedance (Note 2)
Pin Function
Pin Function
25
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