SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 73

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

© 2006 Semtech Corp.
POWER MANAGEMENT
Functional Descriptions
SDA
SCL
SDA
SDA
SCL
SCL
Write to single register (combined format)
Write to single register ('normal' format)
Read from single register (combined format)
SDA and SCL are driven by the Master unless otherwise specified.
SAn = Slave Address (bit n)
RAn = Register Address (bit n)
WDn = Write Data (bit n)
RDn = Read Data (bit n)
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
Slave address (3 LSBs
determined by I2CSlaveAddr
register)
SA
SA
2
2
SA
SA
1
1
SA2
SA
SA
0
0
R/
W
SA1
R/
W
(continued)
SA0
RA
7
RA
7
R/W
RA
6
RA
6
Register Address
RA
5
Register Address
RA
5
RA
4
RA
4
RA7
RA
3
RA
3
RA6
RA
2
I
RA
2
2
C Timing Diagrams
RA
RA5
1
RA
1
RA
Register Address
0
RA
0
RA4
SCL may be briefly held low
(stretched) by SH3100 here
RA3
73
RA2
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
Slave address (3 LSBs
determined by
I2CSlaveAddr register)
RA1
RA0
SA
2
SA
2
SA
1
SA
WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0
1
SA
0
SA
0
R/
W
SCL may be briefly held low
(stretched) by SH3100 here
R/
W
0
SCL may be briefly held low
(stretched) by SH3100 here
RD
7
Write Data
WD
7
RD
Read data driven by SH3100
6
WD
6
RD
5
WD
5
RD
4
Write Data
WD
4
RD
3
WD
3
RD
2
WD
2
RD
1
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WD
1
RD
0
SH3100
WD
0