SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 30

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

© 2006 Semtech Corp.
POWER MANAGEMENT
Register Descriptions
Register Name Clk0Config
Address(hex): 20
CLK0Supply
Bit No.
Bit 7
[2:0]
[7]
[6]
[5]
[4]
Description
CLK0 supply
CLK0 HF/LF
CLK1 = CLK0
CLK0Enable
CLK0 PostScaler
THIS REGISTER IS FUSE
INITIALIZED
CLK0 HF/LF
Bit 6
(continued)
CLK1=CLK0
Bit 5
Description
CLK0Enable
Bit 4
000
001
010
011
100
101
110
111
0
1
0
1
0
1
0
1
Bit Value
30
(R/W) Sets up CLK0
CLK0 pad is supplied by VDD. When VDD drops below VBO,
CLK0 ceases
CLK0 pad is supplied by VBAK
CLK0 is derived from the post-scaled HFDCO
CLK0 is set to 32.768 kHz
CLK1 is treated completely independently from CLK0. Phase
relationship can not be guaranteed
CLK1 is set to run at the same frequency as CLK0, with or
without inversion. CLK1 and CLK0 transition together, and
operate as in-phase or complementary clock outputs
If any interrupt is enabled in the InterruptEnable register, then
setting CLK0 to 0 disables CLK0. The clock resumes whenever
any enabled interrupt activates
CLK0 is enabled unless in AutoClkDetect mode and CLKIN has
stopped
CLK0 frequency = HFDCO frequency
CLK0 frequency = HFDCO/2
CLK0 frequency = HFDCO/4
CLK0 frequency = HFDCO/8
CLK0 frequency = HFDCO/16
CLK0 frequency = HFDCO/32
CLK0 frequency = HFDCO/64
CLK0 frequency = HFDCO/128
This register is ignored if the CLK0 HF/LF bit is set
Note that this register may not be changed if the
App-specificFuseWP bit in the WriteProtects register is set
Bit 3
Value Description
Bit 2
CLK0 post-scaler
Default Value: 0011 0000
Reset Event: P, W (bit 7)
Reset Event: P, W, B (bits 6:0)
Bit 1
www.semtech.com
SH3100
Bit 0