SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 34

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SH3100IMTR

Manufacturer Part Number
SH3100IMTR
Description
Supervisory IC with I2C Interface and PWM
Manufacturer
SEMTECH [Semtech Corporation]
Datasheet
© 2006 Semtech Corp.
POWER MANAGEMENT
Register Descriptions
Register Name ResetDuration
Address(hex): 31
Bit No.
Bit 7
[4:0]
Description
ResetDuration
THIS REGISTER IS FUSE
INITIALIZED
Bit 6
(continued)
Bit 5
Description
Bit Value
Bit 4
34
(R/W) Determines the reset
duration
Value Description
Determines the duration between the deactivation of a reset
event (eg. VDD rises above the VBO level, or watchdog expires)
and the NRST pin becoming deactivated
This register determines the reset duration under the following
conditions:
If the DeviceMode register in ADCConfig register is set to 000,
i.e. ‘Normal’ mode, and the SNSE pin is 1 during startup, then
this register determines the reset duration. (if SNSE=0 on
startup, then reset duration is 6 ms, if SNSE is unconnected,
then reset duration is 270 ms)
If the DeviceMode register is set to any other mode, then this
register determines the reset duration irrespective of the SNSE
pin.
Please note that increasing the value of this register in any
mode except normal (DeviceMode=000) causes a reset.
Note that this register may not be changed if the
App-specificFuseWP bit in the WriteProtects register is set
Bit 3
ResetDuration
Bit 2
Default Value: 0000 0000
Reset Event: P, W
Bit 1
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Bit 0

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