SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 25

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

© 2006 Semtech Corp.
POWER MANAGEMENT
Register Descriptions
Register Name RTC
Register Name RTC
Register Name InterruptEnable
Address(hex): 10
Address(hex): 11
Address(hex): 14
Bit No.
Bit No.
Bit No.
Bit 7
[6:4]
[3:0]
Bit 7
[7:0]
Bit 7
[5]
[4]
[2]
[1]
[0]
Description
Seconds (MSD)
Seconds (LSD)
Description
SubSeconds
Description
SNSE Fault interrupt enable
ADC conversion complete
indicator interrupt enable
RTC alarm interrupt enable
Comparator trigger interrupt
enable
PIT interrupt enable
Bit 6
Bit 6
Bit 6
(continued)
Seconds (MSD)
SNSE Fault
Bit Value
00 (hex)
Bit 5
Bit 5
Bit 5
Description
Description
Description
Value Description
Least significant byte of the RTC, incrementing at 256 Hz from 00 to FF. Note that
this is the only RTC byte which is NOT BCD coded
Writing to this register loads all six bytes of RTC into the counter after up to two
periods of the 256 Hz clock, i.e. 7.8 ms later. It is important that no writes or
reads to either WakeupTime, RTC, PeriodicTimer nor DCOCode occur during this
period
When reading the RTC, this must be the first byte read
ADC Done
Bit Value
Bit Value
00 (hex)
00 (hex)
Bit 4
Bit 4
Bit 4
0
1
0
1
0
1
0
1
0
1
SubSeconds
25
(R/W) Real Time Clock.
Value Description
Upper digit of the Binary Coded Decimal seconds count
Lower digit of the BCD seconds count. Cycles from 00 (BCD) to
59 (BCD)
See also 0B description
(R/W) Real Time Clock.
(R/W) Selects which interrupt
sources generate interrupts
Value Description
SNSE fault interrupts disabled
SNSE fault interrupts enabled
If the DeviceMode fuse (address 18, bits [5:3]) are set for fan
control mode, this bit is automatically set on startup, but it may
be overridden
ADC complete interrupts disabled
ADC complete interrupts enabled
RTC alarm interrupt disabled
RTC alarm interrupt enabled
Comparator interrupt disabled
Comparator interrupt enabled
PIT interrupt disabled
PIT interrupt enabled
Bit 3
Bit 3
Bit 3
RTC Alarm
Bit 2
Bit 2
Bit 2
Seconds (LSD)
Default Value: 0000 0000
Reset Event: P
Default Value: 0000 0000
Reset Event: P
Default Value: 0000 0000
Reset Event: P, W, B
Comparator
trigger
Bit 1
Bit 1
Bit 1
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SH3100
PIT expired
Bit 0
Bit 0
Bit 0