SH3100IMTR SEMTECH [Semtech Corporation], SH3100IMTR Datasheet - Page 19

• Manufacturer Part Number: SH3100IMTR
• Description: Supervisory IC with I2C Interface and PWM
• Manufacturer: SEMTECH [Semtech Corporation]

Each register and register group is described in the fol-
lowing register memory map and subsequent register de-
scription tables.
Register Organization
The SH3100 uses a total of 53 8-bit registers, identifi ed
by a register name and corresponding hexadecimal regis-
ter address. They are presented here in ascending order
by register address. Some registers carry several individ-
ual data fi elds of various sizes; from single-bit values (e.g.
fl ags), upwards. Several data fi elds are spread across
multiple registers, as shown in the register map. Shaded
areas in the map are ‘don’t care’ and writing either 0 or 1
does not affect any function of the device. Cross-hatched
areas denote registers which are initialized at startup
from the on-chip fuse memory.
CAUTION! Do not write to any undefi ned register ad-
dresses, as this may cause the device to operate in a test
mode. If an undefi ned register has been inadvertently ad-
dressed, the device should be reset to ensure the unde-
fi ned registers are at default values.
Register Initialization from Fuses
Some register bits are initialized from the fuse memory
on power-up and following selective reset events. All these
bits can be overwritten by software once the reset signal
NRST has been negated, unless the relevant write-protect
fuse has been set. The fuses defi ne only the default, pow-
er-on state of the device. The registers which are fuse-ini-
tialized are denoted in the register map with cross-hatch-
ing.
© 2006 Semtech Corp.
POWER MANAGEMENT
Register Memory Map
19
Multi-Word Registers
The RTC, PeriodicTimer (PIT), WakeupTime and DCOCode
are multi-byte registers. The least signifi cant byte (LSB)
must be the last of the set to be written, after which their
combined value takes effect. Conversely, the LSB must be
the fi rst byte of these registers to be read.
Because these registers share common resources within
the I
of one of these registers, neither of the others is accessed
for a period to give the internal registers time to update.
After writing to the RTC, subsequent writes to the PIT
should be delayed by at least 4 ms; writes to DCOCode
by a period equal to CLK0; and writes to WakeUpTime by
31μs.
Crystal Trim Write Protect
As an additional measure to protect the crystal loading
capacitance from invalid adjustment, each time the value
of the XtalTrim register is changed, a ‘0’ must fi rst be writ-
ten to the XtalTrimWP register on the preceding access.
Note: If the AppSpecifi cWP bit is set to ‘1’, then the XtalTrim
fuses cannot be written, but unlike other registers the XtalTrim
register CAN still be written - as detailed above.
2
C interface, it is important that after writing the LSB
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SH3100