XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 66

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

GENERAL RELEASE SPECIFICATION
9.5
MOTOROLA
9-10
TIMER CONTROL REGISTER (TCR)
The timer control register is shown in Figure 9-12 performs the following func-
tions:
Reset clears all the bits in the TCR with the exception of the IEDG bit which is
unaffected.
ICIE - INPUT CAPTURE INTERRUPT ENABLE
OCIE - OUTPUT COMPARE INTERRUPT ENABLE
TOIE - TIMER OVERFLOW INTERRUPT ENABLE
TCR
$0012
9B
...
...
B7
B6
BF
...
...
9A
•
•
•
•
This read/write bit enables interrupts caused by an active signal on the PB0/
TCAP pin. Reset clears the ICIE bit.
This read/write bit enables interrupts caused by a successful compare between
the timer counter and the output compare registers. Reset clears the OCIE bit.
This read/write bit enables interrupts caused by a timer overflow. Reset clears
the TOIE bit.
reset:
1 = Input capture interrupts enabled.
0 = Input capture interrupts disabled.
1 = Output compare interrupts enabled.
0 = Output compare interrupts disabled.
1 = Timer overflow interrupts enabled.
0 = Timer overflow interrupts disabled.
Enables input capture interrupts
Enables output compare interrupts
Enables timer overflow interrupts
Control the active edge polarity of the TCAP signal on pin PB0/TCAP
W
R
16
13
17
BIT 7
ICIE
0
SEI
...
...
STA
LDA
STX
...
...
CLI
Figure 9-12. Timer Control Register (TCR)
OCIE
BIT 6
0
OCRH
TSR
OCRL
November 5, 1998
BIT 5
TOIE
16-BIT TIMER
0
DISABLE INTERRUPTS
.....
.....
INHIBIT OUTPUT COMPARE
ARM OCF FLAG FOR CLEARING
READY FOR NEXT COMPARE, OCF CLEARED
.....
.....
ENABLE INTERRUPTS
BIT 4
0
0
BIT 3
0
0
BIT 2
0
0
Unaffected
BIT 1
IEDG
MC68HC05JB3
BIT 0
REV 1
0
0