XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 34

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

GENERAL RELEASE SPECIFICATION
4.3
4.4
4.5
4.5.1 External Interrupt IRQ
MOTOROLA
4-4
RESET INTERRUPT SEQUENCE
The RESET function is not in the strictest sense an interrupt; however, it is acted
upon in a similar manner as shown in Figure 4-2. A low level input on the RESET
pin or an internally generated RST signal causes the program to vector to its start-
ing address which is specified by the contents of memory locations $1FFE and
$1FFF. The I-bit in the condition code register is also set.
SOFTWARE INTERRUPT (SWI)
The SWI is an executable instruction and a non-maskable interrupt since it is exe-
cuted regardless of the state of the I-bit in the CCR. As with any instruction, inter-
rupts pending during the previous instruction will be serviced before the SWI
opcode is fetched. The interrupt service routine address is specified by the con-
tents of memory locations $1FFC and $1FFD.
HARDWARE INTERRUPTS
All hardware interrupts except RESET are maskable by the I-bit in the CCR. If the
I-bit is set, all hardware interrupts (internal and external) are disabled. Clearing
the I-bit enables the hardware interrupts. There are two types of hardware inter-
rupts which are explained in the following sections.
The IRQ pin provides an asynchronous interrupt to the CPU. A block diagram of
the IRQ logic is shown in Figure 4-3.
The IRQ pin is one source of an IRQ interrupt and a mask option can also enable
the four lower Port-A pins (PA0 to PA3) to act as other IRQ interrupt sources.
Refer to Figure 4-3 for the following descriptions. IRQ interrupt source comes
from IRQ latch. The IRQ latch will be set on the falling edge of the IRQ pin or on
any falling edge of PA0-3 pins if PA0-3 interrupts have been enabled. If ‘edge-only’
sensitivity is chosen by a mask option, only the IRQ latch output can activate an
IRQF flag which creates a request to the CPU to generate the IRQ interrupt
sequence. This makes the IRQ interrupt sensitive to the following cases:
If level sensitivity is chosen, the active high state of the signal to the clock input of
the IRQ latch can also activate an IRQF flag which creates an IRQ request to the
CPU to generate the IRQ interrupt sequence. This makes the IRQ interrupt sensi-
tive to the following cases:
1. Falling edge on the IRQ pin.
2. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
1. Low level on the IRQ pin.
2. Falling edge on the IRQ pin.
3. Low level on any PA0-PA3 pin with IRQ enabled (via mask option).
4. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option).
November 5, 1998
INTERRUPTS
MC68HC05JB3
REV 1