XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 61

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

9.3
MC68HC05JB3
REV 1
TCAP
RESET
PB0/
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
INPUT CAPTURE REGISTERS
The input capture function is a technique whereby an external signal (connected
to PB0/TCAP pin) is used to trigger the 16-bit timer counter. In this way it is possi-
ble to relate the timing of an external signal to the internal counter value, and
hence to elapsed time.
Since the TCAP pin is shared with the PB0 I/O pin, changing the state of the PB0
DDR or Data Register can cause an unwanted TCAP interrupt. This can be
avoided by clearing the ICIE bit before changing the configuration of PB0, and
clearing any pending interrupts before enabling ICIE.
The signal on the TCAP pin is first directed to a schmitt trigger or a voltage
comparator as shown in Figure 9-7. Setting the TCMPE bit to “1” will enable the
comparator and the V
CONDITIONING
(bit7 at $0E)
TCMPE
SIGNAL
READ
ICRH
Figure 9-6. Timer Input Capture Block Diagram
& DETECT
SELECT
LOGIC
EDGE
$0012
TIMER CONTROL REG.
DD
/2 reference voltage.
LATCH
November 5, 1998
16-BIT TIMER
ICRH ($0014)
16-BIT COUNTER
INPUT CAPTURE (ICF)
NOTE
NOTE
ICRL ($0015)
TIMER STATUS REG.
GENERAL RELEASE SPECIFICATION
$0013
4
INTERNAL
INTERNAL
DATA
DATA
BUS
BUS
INTERNAL
MOTOROLA
(f
READ
INTERRUPT
ICRL
CLOCK
REQUEST
OSC
TIMER
2)
9-5