XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 55

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

8.3.2 Timer Control/Status Register (TCSR) $08
MC68HC05JB3
REV 1
The TCSR contains the timer interrupt flag bits, the timer interrupt enable bits, and
the real time interrupt rate select bits. Bit 2 and bit 3 are write-only bits which will
read as logical zeros. Figure 8-3 shows the value of each bit in the TCSR follow-
ing reset.
RT0, RT1 — Real-Time Interrupt period select bits
RTIFR — Real Time Interrupt Acknowledge
CTOFR — Timer Overflow Acknowledge
TCNT
$0009
TCSR
$0008
These two bits select the Real-Time Interrupt period and the COP Watchdog
reset period.
The RTIFR is an acknowledge bit that resets the RTIF flag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
The CTOFR is an acknowledge bit that resets the CTOF flag bit. This bit is
unaffected by reset. Reading the CTOFR will always return a logical zero.
reset:
reset:
1 = Clears the RTIF flag bit.
0 = Does not clear the RTIF flag bit.
1 = Clears the CTOF flag bit.
0 = Does not clear the CTOF flag bit.
W
W
R
R
RT1
Figure 8-3. Timer Control/Status Register (TCSR)
0
0
1
1
TMR7
CTOF
BIT 7
BIT 7
Table 8-1. RTI and COP Rates at f
0
0
RT0
0
1
0
1
Figure 8-2. Timer Counter Register
TMR6
BIT 6
BIT 6
RTIF
0
0
Divide Ratio
MULTI-FUNCTION TIMER
2
2
2
2
14
15
16
17
November 5, 1998
CTOFE
TMR5
BIT 5
BIT 5
0
0
Bus Frequency, f
RTI Rate
10.92ms
21.85ms
43.69ms
5.46ms
TMR4
BIT 4
BIT 4
RTIE
0
0
CTOFR
GENERAL RELEASE SPECIFICATION
TMR3
BIT 3
BIT 3
OP
0
0
0
BUS
COP Reset Period
=3.0MHz
=f
349.52ms
(RTI
43.68ms
87.36ms
174.8ms
OP
RTIFR
TMR2
=3.0 MHz
BIT 2
BIT 2
0
0
0
8)
TMR1
BIT 1
BIT 1
RT1
0
1
MOTOROLA
TMR0
BIT 0
BIT 0
RT0
0
1
8-3