XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 3

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

Section
1.1
1.2
1.3
1.4
1.4.1
1.4.2
1.4.3
1.4.4
1.4.5
1.4.6
1.4.7
1.4.8
1.4.9
2.1
2.2
2.3
2.4
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
4.1
4.2
4.3
4.4
MC68HC05JB3
REV 1
FEATURES ...................................................................................................... 1-1
MASK OPTIONS.............................................................................................. 1-2
MCU STRUCTURE.......................................................................................... 1-2
FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4
I/O AND CONTROL REGISTERS ................................................................... 2-2
RAM ................................................................................................................. 2-2
ROM................................................................................................................. 2-2
I/O REGISTERS SUMMARY ........................................................................... 2-3
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A)........................................................................................ 3-2
INDEX REGISTER (X) ..................................................................................... 3-2
STACK POINTER (SP) .................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-2
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
INTERRUPT VECTORS .................................................................................. 4-1
INTERRUPT PROCESSING............................................................................ 4-2
RESET INTERRUPT SEQUENCE .................................................................. 4-4
SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4
V
OSC1, OSC2 ............................................................................................... 1-4
RESET......................................................................................................... 1-6
IRQ .............................................................................................................. 1-6
3.3V ............................................................................................................. 1-6
D+ and D– ................................................................................................... 1-6
PA0-PA7 ...................................................................................................... 1-6
PB0-PB2, PB3-PB7 ..................................................................................... 1-7
PC0-PC3...................................................................................................... 1-7
Half Carry Bit (H-Bit) .................................................................................... 3-3
Interrupt Mask (I-Bit) .................................................................................... 3-3
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-3
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
DD
and V
SS
................................................................................................ 1-4
CENTRAL PROCESSING UNIT
GENERAL DESCRIPTION
TABLE OF CONTENTS
November 5, 1998
INTERRUPTS
SECTION 1
SECTION 2
SECTION 3
SECTION 4
MEMORY
GENERAL RELEASE SPECIFICATION
MOTOROLA
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