XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 36

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

GENERAL RELEASE SPECIFICATION
4.5.3 Port A External Interrupts (PA0-PA3, by mask option)
MOTOROLA
4-6
IRQPU — IRQ pin PUll-up resistor enable
IRQR — IRQ Interrupt Acknowledge
IRQF — IRQ Interrupt Request Flag
IRQE — IRQ Interrupt Enable
The IRQ interrupt can also be triggered by the inputs on the PA0 to PA3 port pins
if enabled by a single mask option. If enabled, the lower four bits of Port A can
activate the IRQ interrupt function, and the interrupt operation will be the same as
for inputs to the IRQ pin. This mask option of PA0-3 interrupt allow all of these
input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins
must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt
sources are also controlled by the IRQE enable bit.
This bit enables/disables the internal pull-up resistor on the IRQ pin.
This write-only bit clears an IRQ interrupt by clearing the IRQ latch, and hence
the IRQF bit. The IRQR bit will always read as a logic zero.
Writing to the IRQF flag bit will have no effect on it. If the additional setting of
IRQF flag bit is not cleared in the IRQ service routine and the IRQE enable bit
remains set the CPU will re-enter the IRQ interrupt sequence continuously until
either the IRQF flag bit or the IRQE enable bit is clear. The IRQF latch is
cleared by reset.
The IRQE bit enables/disables the IRQF flag bit to initiate an IRQ interrupt
sequence.
1 = Internal pull-up resistor in IRQ pin enabled.
0 = Internal pull-up resistor in IRQ pin disabled.
1 = Clears IRQ interrupt request (clears IRQF).
0 = No effect.
1 = Indicates that an IRQ request is pending.
0 = Indicates that no IRQ request triggered by pins PA0-3 or IRQ is
1 = Enables IRQ interrupt, that is, the IRQF flag bit can generate an
0 = The IRQF flag bit cannot generate an interrupt sequence.
pending. The IRQF flag bit can be cleared by writing a logic one to
the IRQR acknowledge bit to clear the IRQ latch and also
conditioning the external IRQ sources to be inactive (if the level
sensitive interrupts are enabled via mask option). Doing so before
exiting the service routine will mask out additional occurrences of
the IRQF.
interrupt sequence. Reset sets the IRQE enable bit, thereby
enabling IRQ interrupts once the I-bit is cleared. Execution of the
STOP or WAIT instructions causes the IRQE bit to be set in order to
allow the external IRQ to exit these modes.
November 5, 1998
INTERRUPTS
MC68HC05JB3
REV 1