XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 64

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

GENERAL RELEASE SPECIFICATION
9.4
MOTOROLA
9-8
Reading the ICRH inhibits further captures until the ICRL is also read. Reading
the ICRL after reading the timer status register (TSR) clears the ICF flag bit. does
not inhibit transfer of the free-running counter. There is no conflict between read-
ing the ICRL and transfers from the free-running timer counters. The input capture
registers always contain the free-running timer counter value which corresponds
to the most recent input capture.
To prevent interrupts from occurring between readings of the ICRH and ICRL, set
the I bit in the condition code register (CCR) before reading ICRH and clear the
I bit after reading ICRL.
OUTPUT COMPARE REGISTERS
The Output Compare function is a means of generating an interrupt when the 16-
bit timer counter reaches a selected value as shown in Figure 9-10. Software
writes the selected value into the output compare registers. On every fourth inter-
nal clock cycle (every eight oscillator clock cycle) the output compare circuitry
compares the value of the free-running timer counter to the value written in the
output compare registers. When a match occurs, the output compare interrupt
flag, OCF is set. A timer interrupt request to the CPU is generated if the output
compare interrupt enable is set, i.e. OCIE=1.
Port pin, PC0 is configured as the OCMP output pin when the OCMPO bit (bit7 at
$06) is set to “1”. The OCMP output reflects the logic of the output compare inter-
rupt flag, OCF, as shown in Figure 9-10.
OCMPO — OCMP Output Enable
Software can use the output compare register to measure time periods, to gener-
ate timing delays, or to generate a pulse of specific duration or a pulse train of
specific frequency and duty cycle.
Writing to the OCRH before writing to the OCRL inhibits timer compares until the
OCRL is written. Reading or writing to the OCRL after reading the TSR will clear
the output compare flag bit (OCF).
DDRC
$0006
reset:
1 = PC0 is OCMP pin, OCF from 16-bit timer output compare.
0 = PC0 is standard I/O pin, from Port-C data register.
W
R
OCMPO
BIT 7
0
VROFF
BIT 6
0
November 5, 1998
BIT 5
16-BIT TIMER
0
NOTE
BIT 4
0
DDRC3
BIT 3
0
DDRC2
BIT 2
0
DDRC1
BIT 1
0
MC68HC05JB3
DDRC0
BIT 0
REV 1
0