XC68HC705JB3 Motorola, XC68HC705JB3 Datasheet - Page 35

• Manufacturer Part Number: XC68HC705JB3
• Description: MICROCONTROLLER
• Manufacturer: Motorola

4.5.2 IRQ Control/Status Register (ICSR) - $0A
MC68HC05JB3
REV 1
PA0
PA1
PA2
PA3
IRQ
The IRQE enable bit controls whether an active IRQF flag can generate an IRQ
interrupt sequence. This interrupt is serviced by the interrupt service routine
located at the address specified by the contents of $1FFA and $1FFB.
If IRQF is set, the only way to clear this flag is by writing a logic one to the IRQR
acknowledge bit in the ICSR. As long as the output state of the IRQF flag bit is
active the CPU will continuously re-enter the IRQ interrupt sequence until the
active state is removed or the IRQE enable bit is cleared.
The IRQ interrupt function is controlled by the ICSR located at $000A. All unused
bits in the ICSR will read as logic zeros. The IRQF bit is cleared and IRQE bit is
set by reset.
ICSR
$000A
Port A External Interrupt
reset:
(Mask Option)
W
R
BIT 7
IRQE
Figure 4-4. IRQ Control and Status Register (ICSR)
1
Figure 4-3. External Interrupt (IRQ) Logic
(Mask Option)
IRQ Level
IRQ VECTOR FETCH
BIT 6
0
0
INTERNAL DATA BUS
November 5, 1998
BIT 5
INTERRUPTS
0
0
RST
V
DD
LATCH
BIT 4
IRQ
0
0
R
IRQ STATUS/CONTROL REGISTER
GENERAL RELEASE SPECIFICATION
BIT 3
IRQF
0
BIT 2
0
0
IRQR
BIT 1
0
0
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST
MOTOROLA
IRQPU
BIT 0
0
4-5