HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 284

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

The IMFA bit of channel 3 is set to 1 for increment pulses and the OVF bit of channel 4 is set to 1
for underflows only. The buffer register (BR) set for the buffer operation is transferred to the GR
upon compare match A3 (when incrementing) or TCNT4 underflow.
GR Setting in Complementary Mode: Be aware of the following when setting the general
registers in complementary PWM mode and when making changes during operation.
• Initial values: Setting H'0000 to T–1 (the initial setting T: TCNT3) is prohibited. After
• Methods of changing settings: Use the buffer operation. Writing directly to general registers
• When changing settings: See figure 10.38.
270 HITACHI
counting starts, this setting is allowed from the point when the first A3 compare match occurs.
may result in incorrect waveform output.
H' 0000
GRA3
GR
GR
BR
Figure 10.38 Example of Changing GR Settings with Buffer Operation (1)
Prohibited