HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 328

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Bits 3 and 2 (group 1 compare-match select 1 and 0 (G1CMS1 and G1CMS0)): G1CMS1 and
G1CMS0 select the ITU channel that triggers TPC output group 1 (TP7–TP4).
Bit 3: G1CMS1
0
1
• Bits 1 and 0 (group 0 compare-match select 1 and 0 (G0CMS1 and G0CMS0)): G0CMS1 and
Bit 1: G0CMS1
0
1
11.2.8
TPMR is an eight-bit read/write register that selects between the TPC's ordinary output and non-
overlap output modes in group units. During non-overlap operation, the output waveform cycle is
set in ITU general register B (GRB) for use as the output trigger and a non-overlap period is set in
general register A (GRA). The output value then changes on compare matches A and B. For
details, see section 11.3.4, TPC Output Non-Overlap Operation. TPMR is initialized to H'F0 on a
reset. It is not initialized in standby mode.
314 HITACHI
G0CMS0 select the ITU channel that triggers TPC output group 0 (TP3–TP0).
Initial value:
Bit name:
TPC Output Mode Register (TPMR)
R/W:
Bit:
Bit 2: G1CMS0
0
1
0
1
Bit 0: G0CMS0
0
1
0
1
—
—
7
1
—
—
6
1
Description
TPC output group 1 (TP7–TP4) output is triggered by
compare-match in ITU channel 0
TPC output group 1 (TP7–TP4) output is triggered by
compare-match in ITU channel 1
TPC output group 1 (TP7–TP4) output is triggered by
compare-match in ITU channel 2
TPC output group 1 (TP7–TP4) output is triggered by
compare-match in ITU channel 3 (initial value)
Description
TPC output group 0 (TP3–TP0) output is triggered by
compare-match in ITU channel 0
TPC output group 0 (TP3–TP0) output is triggered by
compare-match in ITU channel 1
TPC output group 0 (TP3–TP0) output is triggered by
compare-match in ITU channel 2
TPC output group 0 (TP3–TP0) output is triggered by
compare-match in ITU channel 3 (initial value)
—
—
5
1
—
—
4
1
G3NOV G2NOV G1NOV G0NOV
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0