HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 223

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

9.5
1. All registers other than the DMA operations register (DMAOR) and DMA channel control
2. Before rewriting the RS0–RS3 bits of CHCR0–CHCR3, first clear the DE bit to 0 (when
3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the
4. Interrupt during DMAC Transfer
5. The CPU and DMAC leaves the bus right released and the operation of the LSI is stopped
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208 HITACHI
registers 0–3 (CHCR0–CHCR3) should be accessed in word or long word units.
rewriting CHCR with a byte access, be sure to set the DE bit to 0 in advance).
DMAOR will be set.
a. When an NMI interrupt is input, the DMAC stops operation and returns the bus right to the
b. When an interrupt other than an NMI occurs.
when the following conditions are satisfied.
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Countermeasure
Set the warp bit of BCR to 0 and set it to normal mode.
The warp bit (WARP) of the bus control register (BCR) of the bus controller (BSC)is set.
The DMAC is in cycle-steal transfer mode.
The CPU accesses (reads/writes) the on-chip I/O space.
CPU. The CPU then executes the interrupt processing.
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Cautions
When an interrupt is requested from an on-chip peripheral module, the interrupt factor
When an interrupt is requested by IRQ (edge detection), the CPU begins the IRQ
When an interrupt is requested by IRQ (level detection), the IRQ interrupt request
When the DMAC is in burst mode.
The DMAC does not return the bus right to the CPU in burst mode. Therefore, even
when an interrupt is requested in DMAC operation, the CPU cannot get the bus right,
causing the interrupt processing not to be executed. When the DMAC completes
transfer and the CPU gets the bus right, the CPU executes the interrupt processing if the
interrupt requested during DMAC transfer is not cleared.*
* Clear conditions for an interrupt request.
flag is cleared.
interrupt processing of the request source.
signal returned to high level.
When the DMAC is in cycle-steal mode.
The DMAC returns the bus right to the CPU every when the DMAC completes a
transfer unit in cycle-steal mode. Therefore, the CPU executes the requested interrupt
processing when getting the bus right.