HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 358

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

13.2.4
The transmit data register (TDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written
in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible
by writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a reset or in
standby mode.
13.2.5
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a reset or in
standby mode.
•
Bit 7: C/A
0
1
Bit 7 (communication mode (C/A)): C/A selects whether the SCI operates in the asynchronous
or clocked synchronous mode.
Initial value:
Initial value:
Bit name:
Bit name:
Transmit Data Register
Serial Mode Register
R/W:
R/W:
Bit:
Bit:
R/W
R/W
C/A
7
1
7
0
Description
Synchronous mode (initial value)
Clocked synchronous mode
CHR
R/W
R/W
6
1
6
0
R/W
R/W
PE
5
1
5
0
R/W
R/W
O/E
4
1
4
0
STOP
R/W
R/W
3
1
3
0
R/W
R/W
MP
2
1
2
0
CKS1
R/W
R/W
1
1
1
0
HITACHI 345
CKS0
R/W
R/W
0
1
0
0