HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 376

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

Table 13.7 Maximum Bit Rates during External Clock Input (Clocked Synchronous Mode)
2
4
6
8
10
12
14
16
18
20
13.3
13.3.1
The SCI has an asynchronous mode in which characters are synchronized individually, and a
clocked synchronous mode in which communication is synchronized with clock pulses. Serial
communication is possible in either mode. Asynchronous/clocked synchronous mode and the
communication format are selected in the serial mode register (SMR), as shown in table 13.8. The
SCI clock source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and
CKE0 bits in the serial control register (SCR), as shown in table 13.9.
Asynchronous Mode:
• Data length is selectable: seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
• In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors
• An internal or external clock can be selected as the SCI clock source.
(MHz)
preceding selections constitute the communication format and character length.
(ORER), and the break state.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator,
When an external clock is selected, the external clock input must have a frequency 16 times
and can output a serial clock signal with a frequency matching the bit rate.
the bit rate. (The on-chip baud rate generator is not used.)
Operation
Overview
External Input Clock (MHz)
0.3333
0.6667
1.0000
1.3333
1.6667
2.0000
2.3333
2.6667
3.0000
3.3333
Maximum Bit Rate (bits/s)
333333.3
666666.7
1000000.0
1333333.3
1666666.7
2000000.0
2333333.3
2666666.7
3000000.0
3333333.3
HITACHI 363