HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 245

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

• Bit 2 (buffer mode A4 (BFA4)): BFA4 selects the buffer mode for GRA4 and BRA4 in
Bit 2: BFA4
0
1
• Bit 1 (buffer mode B3 (BFB3)): BFB3 selects the buffer mode for GRB3 and BRB3 in channel
Bit 1: BFB3
0
1
• Bit 0 (buffer Mode A3 (BFA3)): BFA3 selects the buffer mode for GRA3 and BRA3 in
Bit 0: BFA3
0
1
10.2.5
The timer output control register (TOCR) is an eight-bit read/write register that inverts the output
level of the complementary PWM mode/reset-synchronized PWM mode. Setting bits OLS3 and
OLS4 is valid in only the complementary PWM mode and reset-synchronized PWM mode. In
other output situations, these bits are ignored. The TOCR is initialized to H'FF or H'7F by a reset
or in the standby mode.
Note: Undefined
• Bits 7–2 (reserved): Bit 7 is read as undefined. Bits 6–2 are always read as 1. The write value
channel 4.
3.
channel 3.
to bit 7 should be 0 or 1. The write value to bits 6–2 should always be 1.
Initial value:
Bit name:
Timer Output Control Register (TOCR)
R/W:
Bit:
—
—
7
*
Description
GRA4 operates normally in channel 4 (initial value)
GRA4 and BRA4 operate in buffer mode in channel 4
Description
GRB3 operates normally in channel 3 (initial value)
GRB3 and BRB3 operate in buffer mode in channel 3
Description
GRA3 operates normally in channel 3 (initial value)
GRA3 and BRA3 operate in buffer mode in channel 3
—
—
6
1
—
—
5
1
—
—
4
1
—
—
3
1
—
—
2
1
OLS4
R/W
1
1
HITACHI 231
OLS3
R/W
0
1