HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 12

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10 Bus Arbitration .................................................................................................................. 157
8.11 Usage Notes ....................................................................................................................... 161
Section 9 Direct Memory Access Controller (DMAC)
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
8.2.9
8.2.10 Parity Control Register (PCR).............................................................................. 112
8.2.11 Notes on Register Access ..................................................................................... 114
Address Space Subdivision................................................................................................ 115
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
Accessing External Memory Space ................................................................................... 128
8.4.1
8.4.2
8.4.3
DRAM Interface Operation ............................................................................................... 134
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
Address/Data Multiplexed I/O Space Access.................................................................... 151
8.6.1
8.6.2
8.6.3
Parity Check and Generation ............................................................................................. 154
Warp Mode........................................................................................................................ 154
Wait State Control ............................................................................................................. 155
8.10.1 The Operation of Bus Arbitration ........................................................................ 158
8.10.2 BACK Operation.................................................................................................. 159
8.11.1 Usage Notes on Manual Reset.............................................................................. 161
8.11.2 Usage Notes on Parity Data Pins DPH and DPL ................................................. 164
8.11.3 Maximum Number of States from BREQ Input to Bus Release ......................... 164
Wait State Control Register 1 (WCR1)................................................................ 98
Wait State Control Register 2 (WCR2)................................................................ 101
Wait State Control Register 3 (WCR3)................................................................ 103
DRAM Area Control Register (DCR).................................................................. 104
Refresh Control Register (RCR) .......................................................................... 107
Refresh Timer Control/Status Register (RTCSR) ................................................ 108
Refresh Timer Counter (RTCNT) ........................................................................ 110
Refresh Time Constant Register (RTCOR).......................................................... 112
Address Spaces and Areas.................................................................................... 115
Bus Width............................................................................................................. 117
Chip Select Signals (CS0–CS7)............................................................................ 117
Shadows................................................................................................................ 118
Area Description .................................................................................................. 120
Basic Timing ........................................................................................................ 128
Wait State Control................................................................................................ 129
Byte Access Control ............................................................................................. 133
DRAM Adress Multiplexing ............................................................................... 134
Basic Timing ........................................................................................................ 136
Wait State Control................................................................................................ 138
Byte Access Control ............................................................................................. 140
DRAM Burst Mode.............................................................................................. 142
Refresh Control .................................................................................................... 148
Basic Timing ........................................................................................................ 152
Wait State Control................................................................................................ 153
Byte Access Control ............................................................................................. 153
............................................ 169