HD6417021 Hitachi Semiconductor, HD6417021 Datasheet - Page 444

• Manufacturer Part Number: HD6417021
• Description: SuperH RISC engine
• Manufacturer: Hitachi Semiconductor

• Bits 5–0 (reserved): Bit 5 is a read-only bit that always reads as 0. Only write 0 to bit 5.
18.3
18.3.1
Execution of the SLEEP instruction when the standby bit (SBY) in the standby control register
(SBYCR) is cleared to 0 causes a transition from the program execution state to the sleep mode.
Although the CPU halts immediately after executing the SLEEP instruction, the contents of its
internal registers remain unchanged. The on-chip peripheral modules do not halt in the sleep
mode.
18.3.2
The sleep mode is canceled by an interrupt, DMA address error, power-on reset, or manual reset.
Cancellation by an Interrupt: When an interrupt occurs, the sleep mode is canceled and interrupt
exception processing is executed. The sleep mode is not canceled if the interrupt cannot be
accepted because its priority level is equal to or less than the mask level set in the CPU’s status
register (SR). Likewise, the sleep mode is not canceled if the interrupt is disabled by the on-chip
peripheral module.
Cancellation by a DMA Address Error: If the DMAC operates during the sleep mode and a
DMA address error occurs, the sleep mode is canceled and DMA address error exception-
processing is executed.
Cancellation by a Power-On Reset: If the RES signal goes low while the NMI signal is high, the
sleep mode is canceled and the power-on reset state is entered. If the NMI signal is brought from
low to high in order to set the LSI for power-on resets, an NMI interrupt will occur whenever the
rising edge of the NMI is selected as the valid edge (in NMI edge select bit NMIE of the interrupt
control register ICR of the interrupt controller). When this occurs, the NMI interrupt cancels the
sleep mode.
Cancellation by a Manual Reset: If the RES signal goes low while the NMI signal is low, the
sleep mode is canceled and the manual reset state is entered. If the NMI signal is brought from
high to low in order to set the LSI for manual resets, the sleep mode will be canceled by an NMI
interrupt whenever the falling edge of the NMI is selected as the valid edge (in the NMIE bit).
Writing to bits 4–0 is disabled. These bits always read 1.
Sleep Mode
Transition to the Sleep Mode
Canceling the Sleep Mode
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