M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 42
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M52S64322A-10BG
Manufacturer Part Number
M52S64322A-10BG
Description
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S64322A-10BG.pdf
(47 pages)
- Current page: 42 of 47
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ESMT
Deep Power Down Mode Entry & Exit Cycle
Note:
DEFINITION OF DEEP POWER MODE FOR Mobile SDRAM:
Deep Power Down Mode is an operating mode to achieve maximum power reduction by cutting the power of the whole memory
of the device. Once the device enters in Deep Power Down Mode, data will not be retained. Full initialization is required when
the device exits from Deep Power Down Mode.
TO ENTER DEEP POWER DOWN MODE
1) The deep power down mode is entered by having CS and WE held low with RAS and CAS high at the rising edge of
2) Clock must be stable before exited deep power down mode.
3) Device must be in the all banks idle state prior to entering Deep Power Down mode.
TO EXIT DEEP POWER DOWN MODE
4) The deep power down mode is exited by asserting CKE high.
5) 200 μ s wait time is required to exit from Deep Power Down.
6) Upon exiting deep power down an all bank precharge command must be issued followed by two auto refresh commands
Elite Semiconductor Memory Technology Inc.
the clock. While CKE is low.
and a load mode register sequence.
Publication Date: Aug. 2009
Revision: 1.3
M52S64322A
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