F25L32PA-100PAG ESMT [Elite Semiconductor Memory Technology Inc.], F25L32PA-100PAG Datasheet
F25L32PA-100PAG
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F25L32PA-100PAG Summary of contents
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... F25L32PA –100PHG 100MHz GENERAL DESCRIPTION The F25L32PA is a 32Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard and Dual Serial Peripheral Interface (SPI). ESMT’s memory devices reliably store memory data even after 100,000 programming and erase cycles. ...
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... SOIC HOLD SIO 1 Elite Semiconductor Memory Technology Inc F25L32PA HOLD 7 6 SCK SIO 0 SCK SIO Publication Date: Mar. 2009 Revision: 1 ...
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... The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. To temporality stop serial communication with SPI flash memory without resetting the device. To provide power. Page Address Memory Array Page Buffer Y-Decoder Byte Address Latch / Counter Serial Interface HOLD (SIO ) (SIO ) 0 1 F25L32PA Functions Publication Date: Mar. 2009 Revision: 1.0 3/36 ...
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... ESMT SECTOR STRUCTURE Table 1: F25L32PA Sector Address Table Block Sector 1023 63 : 1008 1007 62 : 992 991 61 : 976 975 60 : 960 959 59 : 944 943 58 : 928 927 57 : 912 911 56 : 896 895 55 : 880 879 54 : 864 863 53 : 848 847 52 : 830 831 51 : 816 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32PA Sector Address Table – Continued I Block Sector 815 50 : 800 799 49 : 784 783 48 : 768 767 47 : 752 751 46 : 736 735 45 : 720 719 44 : 704 703 43 : 688 687 42 : 672 671 41 : 656 655 40 : 640 639 39 : 624 623 38 : 608 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32PA Sector Address Table – Continued II Block Sector 607 37 : 592 591 36 : 576 575 35 : 560 559 34 : 544 543 33 : 528 527 32 : 512 511 31 : 496 495 30 : 480 479 29 : 464 463 28 : 448 447 27 : 432 431 26 : 416 415 25 : 400 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32PA Sector Address Table – Continued III Block Sector 399 24 : 384 383 23 : 368 367 22 : 352 351 21 : 336 335 20 : 320 319 19 : 304 303 18 : 288 287 17 : 272 271 16 : 256 255 15 : 240 239 14 : 224 223 13 : 208 207 12 : 192 Elite Semiconductor Memory Technology Inc. ...
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... ESMT Table 1: F25L32PA Sector Address Table – Continued IV Block Sector 191 11 : 176 175 10 : 160 159 9 : 144 143 8 : 128 127 7 : 112 111 Elite Semiconductor Memory Technology Inc. Sector Size Address range (Kbytes) 4KB 0BF000H – ...
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... BUSY The BUSY bit determines whether there is an internal Erase or Program operation in progress. A “1” for the BUSY bit indicates the device is busy with an operation in progress. A “0” indicates the device is ready for the next valid operation. F25L32PA Default at Read/Write Power-up 0 ...
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... BP2, BP1, BP0 bits as long high or the Block- Protection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1. Elite Semiconductor Memory Technology Inc. Table 3: F25L32PA Block Protection Table Status Register Bit BP2 BP1 BP0 ...
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... The HOLD function is only available for Standard and Dual SPI operation ctive Ho ld Table 4: Conditions to Execute Write-Status- Register (WRSR) Instruction BPL Execute WRSR Instruction F25L32PA Hold condition. To resume A ctive Not Allowed Allowed Allowed Publication Date: Mar. 2009 Revision: 1.0 11/36 ...
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... D OUT Hi Hi Hi F25L32PA 1~3 Bus Cycle OUT IN OUT IN OUT Hi Hi OUT0 Hi Hi cont OUT0 Hi-Z A ...
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... OUT1 , Bus Cycle-3 F25L32PA 1~3 Bus Cycle OUT IN OUT IN OUT 20H X 16H - - 00H Hi-Z X 8CH X Hi-Z 01H Hi-Z X 15H ...
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... ADD. ADD. ADD. X MSB MSB F25L32PA - must remain active N+1 N+2 N+3 N ...
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... Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence Dummy ADD. ADD. ADD. MSB HIGH IMPENANCE F25L32PA switches from In put to Ouput ...
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... 23- 16 15- 8 7-0 7 AxH F25L32PA – “AxH”, the next Fast Read Dual I/O instruction (after 7 0 –M ] are the value other than “AxH”, the next 7 0 –M ] before issuing normal instructions ...
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... After the Page Program cycle has 7 0 finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 10 for the Page Program sequence. F25L32PA Publication Date: Mar. 2009 Revision: 1.0 17/36 ...
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... SPI instruction. See Figure 16 for the Mode Bit Reset instruction. Mode bit Reset for Dual I F25L32PA – “AxH”, the device will not recognize any standard SPI Publication Date: Mar. 2009 Revision: 1.0 – ...
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... Erase cycle. See Figure 18 for the Sector Erase sequence Address bits ADD. MSB MSB HIGH IMPENANCE F25L32PA - Most Significant address) are must be driven high before the IL IH for the completion of the ...
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... CE . See Figure 20 for the RDSR instruction sequence HIGH IMPEDANCE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB Status Register Data Out F25L32PA for the completion of the internal self-timed Publication Date: Mar. 2009 Revision: 1.0 20/36 ...
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... CE must be driven high before the WRDI instruction is executed MODE3 SCK MODE0 04 SI MSB HIGH IMPENANCE SO instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. F25L32PA Publication Date: Mar. 2009 Revision: 1.0 21/36 ...
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... WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6. F25L32PA Publication Date: Mar. 2009 Revision: 1.0 22/36 ...
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... RES1 The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status of OTP. F25L32PA ). See Figure 25 for the Deep Power SB1 T DP Deep Power Down Current ...
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... SS 3 Dummy Bytes Table 6: Electronic Signature Data Mode Normal In secured OTP mode & non lock down (OTP_lock =0) In secured OTP mode & lock down (OTP_lock =1) F25L32PA T RES1 Standby Current (I ) SB2 Electronic-Signature Data Out MSB ...
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... ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 20H, identifies the memory type as SPI Flash. Byte3, 16H, identifies the device as F25L32PA. The instruction sequence is shown in Figure 28 1415 1617 1819 2021 2627 2829 3031 ...
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... ESMT Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as F25L32PA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, ...
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... A Limits Min Max Standard 15 Dual 18 Standard 20 Dual 23 Standard 23 Dual 25 Standard 25 Dual 0.8 0 0.2 V -0.2 DD F25L32PA Value Unit ℃ Test Condition Unit mA CE =0 SO=open =0 SO=open =0 SO=open =0 SO=open DD DD ...
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... MHz, other pins open) Description Normal 33 MHz Min Max 100 F25L32PA Unit Test Method mA JEDEC Standard 78 Minimum 10 10 Test Condition OUT Fast 50 MHz Fast 86 MHz Min Max Min Max 50 86 ...
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... Symbol 2 Typ Max T 90 300 1 100 100,000 - 20 - F25L32PA Fast 86 MHz Fast 100 MHz Min Max Min Max 1.8 1.8 Unit Cycles Years Publication Date: Mar. 2009 Revision: 1.0 ...
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... ESMT Figure 30: Serial Input Timing Diagram Figure 31: Serial Output Timing Diagram Elite Semiconductor Memory Technology Inc. F25L32PA Publication Date: Mar. 2009 Revision: 1.0 30/36 ...
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... Elite Semiconductor Memory Technology Inc Program, Erase and Write command is ignored CE must track V CC (min) T Reset VSL State PUW Threshold WI Symbol Min. T 200 VSL T PUW F25L32PA Read command Device is fully is allowed accessible Time Max. Unit Publication Date: Mar. 2009 Revision: 1.0 31/36 ...
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... Figure 34: AC Input/Output Reference Waveforms Figure 35: A Test Load Example Elite Semiconductor Memory Technology Inc. Input timing reference level 0.7VCC Measurement 0.3VCC Note : Input pulse rise and fall time are <5ns F25L32PA Output timing reference level AC 0.5VCC Level Publication Date: Mar. 2009 Revision: 1.0 32/36 ...
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... E 0.002 0.006 0.010 E 1 0.067 0.071 0.075 L 0.014 0.016 0.020 e 0.007 0.008 0.010 L 1 θ 0.202 0.206 0.210 F25L32PA L L1 DETAIL "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 7.70 7.90 8.10 0.303 0.311 5.18 5.28 5.38 0.204 0.208 0.50 0.65 0.80 0.020 0.026 1 ...
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... E 0.004 --- 0.012 E 1 0.081 --- --- L 0.012 --- 0.020 e θ 0.008 --- 0.013 0.400 0.406 0.413 F25L32PA GAUGE PLANE L DETAIL "X" "X" Dimension in mm Dimension in inch Min Norm Max Min Norm 10.30 BSC 0.406 BSC 7.50 BSC 0.295 BSC 0.40 --- 1.27 0.016 1.27 BSC 0.050 BSC ° 0 ° ...
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... Elite Semiconductor Memory Technology Inc. Date 2008.11.21 Original 1. Modify the specification of T 2009.01.09 2. Modify headline 1. Add Dual SPI instructions 2. Modify the memory type of JEDEC Read-ID data from 2009.03.16 40H to 20H 3. Delete the rating of Temperature Under Bias F25L32PA Description CE Publication Date: Mar. 2009 Revision: 1.0 35/36 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice F25L32PA Publication Date: Mar. 2009 Revision: 1.0 36/36 ...