M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 12
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M52S64322A-10BG
Manufacturer Part Number
M52S64322A-10BG
Description
512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
Manufacturer
ESMT [Elite Semiconductor Memory Technology Inc.]
Datasheet
1.M52S64322A-10BG.pdf
(47 pages)
DEVICE OPERATIONS (Continued)
BANK ACTIVATE
The bank activate command is used to select a random row
in an idle bank. By asserting low on RAS and CS with
desired row and bank address, a row access is initiated. The
read or write operation can occur after a time delay of t
(min)
timing parameter of SDRAM, therefore it is dependent on
operating clock frequency. The minimum number of clock
cycles required between bank activate and read or write
command should be calculated by dividing t
cycle time of the clock and then rounding of the result to the
next higher integer. The SDRAM has four internal banks in
the same chip and shares part of the internal circuitry to
reduce chip area, therefore it restricts the activation of four
banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high requiring some time
for power supplies to recover before another bank can be
sensed reliably. t
required between activating different bank. The number of
clock cycles required between different bank activation must
be calculated similar to t
required for the bank to be active to initiate sensing and
restoring the complete row of dynamic cells is determined by
t
satisfy t
to that active bank can be asserted. The maximum time any
bank can be in the active state is determined by t
t
BURST READ
The burst read command is used to access burst of data on
consecutive clock cycles from an active row in an active
bank. The burst read command is issued by asserting low on
of the clock. The bank must be active for at least t
before the burst read command is issued. The first output
appears in CAS latency number of clock cycles after the
issue of burst read command. The burst length, burst
sequence and latency from the burst read command is
determined by the mode register which is already
programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the
initial address does not start from a boundary such that
number of outputs from each I/O are equal to the burst
length programmed in the mode register. The output goes
into high-impedance at the end of burst, unless a new burst
read was initiated to keep the data output gapless. The burst
read can be terminated by issuing another burst read or
burst write in the same bank or the other active bank or a
precharge command to the same bank. The burst stop
command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command
and is used to write data into the SDRAM on consecutive
clock cycles in adjacent addresses depending on burst
length
Elite Semiconductor Memory Technology Inc.
CS and RAS with WE being high on the positive edge
RAS
RAS
(max) can be calculated similar to t
from the time of bank activation. t
(min). Every SDRAM bank activate command must
RAS
(min) specification before a precharge command
RRD
(min) specifies the minimum time
RCD
specification. The minimum time
RCD
RCD
specification.
is the internal
RCD
RAS (max)
(min) with
RCD
(min)
and
RCD
and burst sequence. By asserting low on CS , CAS
and WE with valid column address, a write burst is
initiated. The data inputs are provided for the initial
address in the same clock cycle as the burst write
command. The input buffer is deselected at the end of
the burst length, even though the internal writing can be
completed yet. The writing can be complete by issuing a
burst read and DQM for blocking data inputs or burst
write in the same or another active bank. The burst stop
command is valid at every burst length. The write burst
can also be terminated by using DQM for blocking data
and procreating the bank t
be written into the active row. See DQM OPERATION
also.
DQM OPERATION
The DQM is used mask input and output operations. It
works similar to OE during operation and inhibits
writing during write operation. The read latency is two
cycles from DQM and zero cycle for write, which means
DQM masking occurs two cycles later in read cycle and
occurs in the same cycle during write cycle. DQM
operation is synchronous with the clock. The DQM
signal is important during burst interrupts of write with
read or precharge in the SDRAM. Due to asynchronous
nature of the internal write, the DQM operation is critical
to avoid unwanted or incomplete writes when the
complete burst write is required. Please refer to DQM
timing diagram also.
PRECHARGE
The precharge is performed on an active bank by
asserting low on clock cycles required between bank
activate and clock cycles required between bank
activate and CS , RAS , WE and A10/AP with valid
BA0~BA1 of the bank to be procharged. The precharge
command can be asserted anytime after t
satisfy from the bank active command in the desired
bank. t
cycles required to complete row precharge is calculated
by dividing t
the next higher integer. Care should be taken to make
sure that burst write is completed or DQM is used to
inhibit writing before precharge command is asserted.
The maximum time any bank can be active is specified
by t
the end of precharge, the bank enters the idle state and
is ready to be activated again. Entry to power-down,
Auto refresh, Self refresh and Mode register set etc. is
possible only when all banks are in idle state.
RAS (max)
RP
is defined as the minimum number of clock
. Therefore, each bank activate command. At
RP
with clock cycle time and rounding up to
Publication Date: Aug. 2009
Revision: 1.3
RDL
after the last data input to
M52S64322A
RAS
12/47
(min) is