M52S64322A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52S64322A-10BG Datasheet - Page 23

• Manufacturer Part Number: M52S64322A-10BG
• Description: 512K x 32 Bit x 4 Banks Mobile Synchronous DRAM
• Manufacturer: ESMT [Elite Semiconductor Memory Technology Inc.]

ESMT
8. Burst Stop & Interrupted by Precharge
9. MRS
*Note:
Elite Semiconductor Memory Technology Inc.
1. t
2. Number of valid output data after burst stop: 1, 2 for CAS latency = 2, 3 respectiviely.
3. Write burst is terminated. t
4. DQM asserted to prevent corruption of locations D2 and D3.
5. Precharge can be issued here or earlier (satisfying t
6. PRE: All banks precharge, if necessary.
DQ ( C L 2 )
D Q ( C L 3 )
Read or write burst stop command is valid at every burst length.
MRS can be issued only at all banks precharge state.
BDL
CM D
C L K
DQ M
C M D
CL K
DQ
: 1 CLK; Last data in to burst stop delay.
C M D
C L K
1 ) W r i t e B u r s t S t o p ( B L = 8 )
2 ) R e a d B u r s t S t o p ( B L = 4 )
1 ) M o d e R e g i s t e r S e t
W R
D 0
RD
P R E
D1
*N o t e 6
S T O P
Q 0
D2
RDL
t
R P
determinates the last data write.
Q 0
D 3
Q 1
t
B D L
* N o t e 2
S T O P
M RS
D 4
Q 1
* N o t e 1
* N o t e 2
2 C L K
D5
A C T
D Q ( C L 2 )
D Q ( CL 3 )
RAS
CM D
C L K
DQ M
C M D
CL K
DQ
min delay) with DQM.
2 ) R e a d i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
1 ) W r i t e i n t e r r u p t e d b y p r e c h a r g e ( B L = 4 )
W R
R D
D 0
D1
t
M a s k M a s k
R D L
Q 0
Publication Date: Aug. 2009
P R E
Revision: 1.3
Q 0
Q 1
* N o t e 3
* N o t e 4
P R E
Q 1
Q 2
M52S64322A
* N o t e 5
Q 3
Q 2
Q 3
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