GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 88

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
H_Feedback_Divide
H_Reference_Divide
PCLK1_Phase/Divide
Address
29h-28h
2Bh-2Ah
2Ch
2Ch
2Ch
2Ch
2Ch
36655 - 2
31-0
Bit
31-0
15-7
6
5-2
1
0
April 2006
In the internal video genlock block, this register defines
In the internal video genlock block, this register defines
Description
the numerator of the divide ratio.
This register may be programmed to manually genlock
the output to the input reference.
The default value of this register will vary depending on
the output video standard selected.
Address 28h = bits 15-0
Address 29h = bits 31-16
Reference:
the denominator of the divide ratio.
This register may be programmed to manually genlock
the output to the input reference.
The default value of this register will vary depending on
the output video standard selected.
Address 2Ah = bits 15-0
Address 2Bh = bits 31-16
Reference:
Reserved. Set these bits to zero when writing to 2Ch.
Current_P1 - selects the current drive capability of the
PCLK1 pin. Set this bit HIGH for high current drive.
Otherwise, the current drive will be low.
NOTE: The current drive should be set high if PCLK1 is
greater than 100MHz.
Reference:
PCLK1_Phase - adjusts the output phase of the PCLK1
clock with respect to the timing output pins. Phase is
delayed in 700ps (nominal) increments as shown in
Table
Reference:
Divide_By_4 - set this bit HIGH to divide the output
PCLK1 by four.
NOTE: Setting this bit and bit 0 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
Divide_By_2 - set this bit HIGH to divide the output
PCLK1 by two.
NOTE: Setting this bit and bit 1 simultaneously HIGH
will hold the PCLK1 pin LOW.
Reference:
3-6.
Section 3.6.2.1 on page 54
Section 3.6.2.1 on page 54
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
Section 3.7.1 on page 61
GS4911B/GS4910B Data Sheet
R/W
R/W
R/W
–
R/W
R/W
R/W
R/W
Default
–
–
–
0
0
0
0
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