GS9020A Gennum Corporation, GS9020A Datasheet
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GS9020A
Specifications of GS9020A
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GS9020A Summary of contents
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... GS9035A Reclocker or the GS9025A Receiver, thus providing a complete high performance, digital video input processor with EDH, digital sync signal generation, and other system features. The GS9020A also includes a parallel to serial converter and NRZI compliant data output. The EDH core implements EDH insertion and extraction according to SMPTE RP-165 ...
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PARALLEL TO SDO 0 BUF CONVERTER 1 SDO WITH SCRAMBLER SDI BUF SDI SCI BUF PRESCALER SCI 19922 - 3 SERIAL DESCRAMBLER DATA [9:0] 10 SERIAL TO PARALLEL SYNC CONVERTER DETECTOR PCLK OUT ALIGNING SCRAMBLER CONTROL UNIT RESET BLOCK DIAGRAM ...
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ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range (any input) Operating Temperature Range Storage Temperature Lead Temperature (soldering, 10 sec) DC ELECTRICAL CHARCTERISTICS 70°C unless otherwise shown PARAMETER SYMBOL ...
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... The serial clock rising edge should occur at the centre of the data period for optimum performance. (See Figure 1) 2. Since the GS9020A does not have a parallel clock input not possible to define timing details relative to it. Instead the GS9020A has a parallel clock output and all timing information is relative to PCLKOUT. The flag port pins (FL[4:0], F_R/W, S[1:0]) are the only inputs where the timing details are important ...
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... A[2:0]/P[2:0] I GS9020A TOP VIEW DESCRIPTION Differential serial data inputs. Differential serial clock inputs. Host interface mode select. When HIGH, the host interface is configured for I²C mode. When LOW, the host interface is configured for parallel port mode ...
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... CS I Parallel port chip select. When CS is LOW and R/W is HIGH, the GS9020A drives the address/ data bus. When CS is LOW and R/W is LOW, the user should drive the address/data bus. When CS is HIGH, the address/data bus high impedance state (Hi - Z). In I²C mode, this pin must be set HIGH ...
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PIN DESCRIPTIONS NUMBER SYMBOL TYPE 78 CLIP_TRS I 79 TRS_ERR O 80 ANC_DATA VDD GND 69 SVDD 72 SGND 5, 8 VDD_SDI, SDI 9, 12 VDD_SCI, SCI 29,51,68 VDD 30,50,67 GND 10 FRAMED ...
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... The internal pullup resistors allow the GS9020A to be easily interfaced to the GS9025A as shown in Figure 5 and Figure 17. An external diode is required to offset the input signals to the input range of the GS9020A. For maximum signal integrity the GS9025A and GS9020A should be placed as close together as possible. ...
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The serial data output circuits are shown in Figure 6. The serial data outputs are designed to drive 50-75Ω controlled impedance traces and can be easily connected to the GS9028 cable driver as shown in Figure 7 and Figure 18. ...
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... FLYWDIS is available as an input pin and as a bit in the HOSTIF write table. The SWITCHFLYW control signal is used in applications where the data input to the GS9020A is switched between two synchronous signals. In this case, the two signals may be slightly misaligned and would normally require the flywheel to completely re-synchronize ...
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... EDH packet. The OUTGOING ERROR FLAGS represent the EDH error flags present in the outgoing EDH packet (after modification by the GS9020A). Please note that the EDH flags can also be accessed using the flag port as described later. The INCOMING and OUTGOING ERROR FLAGS, the incoming Validity bits (FFV and APV), and the EDH_CHKSM bit can be made " ...
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... HIGH, the GS9020A overwrites the reserved words in the OUTGOING EDH packet with those specified in the HOSTIF write table. If RO_CTRL is LOW, the GS9020A does not alter the reserved words. RO_CTRL is a control bit in the HOSTIF write table. The reserved words of the INCOMING EDH packet are also available via the HOSTIF read table ...
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... PIN ANC_CHKSM ANC_DATA EDH_CHKSM The ANC_DATA signal is set HIGH when an ancillary data packet is exiting the GS9020A. This pin is asserted from the start of the first header word through to the end of the checksum word of the ANC packet, inclusive, as shown in If the Figure 10. ...
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... When the F_R/W pin is LOW, the flag port is in write mode and the FL[4:0] pins are configured as inputs. After writing to the flag port, the GS9020A inserts the written flags into the next outgoing EDH packet. Note that external flag overwriting via the flag port takes precedence over HOSTIF overwriting but the flag port writing only affects the next outgoing EDH packet ...
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... The output EDH chip updates the CRC values to correctly reflect the newly modified data. To prevent the output EDH chip from indicating erroneous CRC errors on each field, the GS9020A has two special modes of operation, CRC_MODE and FLAG_MAP mode. 3.11.1 CRC_MODE ...
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... FL[4:0] and S[1:0] pins of the FLAG PORT become FEN outputs and can be connected to the chip which you wish the GS9020A to write the FLAG data to. In this mode the GS9020A automatically increments the value of S[1:0] and subsequently displays the appropriate flags on the FL[4:0] port, synchronous to the rising edge of PCLKOUT. This is illustrated in Figure 12d ...
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... TRS_INSERT bit of the HOSTIF write table. Note that for proper TRS insertion, the incoming standard must be detected and the flywheel synchronized. That is, the GS9020A does NOT provide proper TRS insertion for unformatted video data (video without TRS words LOGIC OPR ...
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... ANC headers are remapped to 3FF in the output data stream. For example bit data is input to the device, the ANC header of 00, FF, FF will appear as 000, 3FC, 3FC and will be remapped to 000, 3FF, 3FF by the GS9020A. 19922 - 3 5.0 HOST INTERFACE TABLES PIN ...
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... AC timing tables, are relative to this edge HOST BIT and must be met (see Figure 14a) C) The GS9020A drives the P[7:0] bus when the R/W pin is HIGH and the CS pin is LOW. At all other times, the P[7:0] port high impedance state. The host interface enable and disable times are shown in Figure 14b and are specified in the AC timing information ...
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... Figure 16a illustrates the reset circuitry. The internal power-on reset circuit of the GS9020A is sensitive to the rise time of the power supply, hence an external power on reset chip or board level reset line is strongly recommended. ...
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... PCLKOUT t OD Fig. 3 Output Delay & Hold Times (Synchronous Outputs GS9025A SDO SDO SCO SCO Fig. 5 Interfacing the GS9020A to the GS9025A V DD GS9025A SDO SDO SCO SCO SYNCHRONOUS INPUTS PCLKOUT Fig. 2 Input Setup & Hold Times (Synchronous Inputs SDI ...
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OS OH PCLKOUT 3FF DOUT [9:0] F [2: PCLKOUT DOUT [9:0] 3FF F [2:0] H PCLKOUT DOUT[9:0] 3FF 000 FIFO_RESET Fig. 9a FIFO_RESET Pulse Timing for Component Signals (FIFOE PCLKOUT ...
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PCLKOUT DOUT[9:0] 3FF FIFO_RESET Fig. 9c FIFO_RESET Pulse Timing for Composite Signals (FIFOE PCLKOUT DOUT[9:0] 000 3FF ANC_DATA Fig. 10a ANC_DATA Timing for Component Signals PCLKOUT DOUT[9:0] 3CF DID ANC_DATA Fig. 10b ANC_DATA Timing for Composite ...
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... F_R//W XX FL[4:0] PCLKOUT S[1:0] F_R/W FL [4:0] t FDIS PCLKOUT Fig. 12b Flag Port Disable Time PCLKOUT X F_R/W FLAGMAP FL[4: S[1: GS9020A GS9021A CRC_MODE = 0 R (GS9021A) 19922 - 3 WRITE CYCLE FF AP ANC Fig ...
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... S [1:0] 7 Fig. 13b Example of FLAG_MAP Mode Implementation [7:0] A/D R/W CS Fig. 14a HOSTIF Parallel Port Input Setup & Hold Times t HEN P[7:0] GS9020A DRIVING R/W CS Fig. 14b HOSTIF Parallel Port Output Enable & Disable Times GS9021A FLAG MAP = 0 F_R HDIS 19922 - 3 ...
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WRITE CYCLE P[7:0] ADDRESS R/W A/D CS FIELD 0 SDI/SDI EDH DOUT[9:0] INTERNAL POWER on RESET CELL RESET PIN t RESET Fig. 16a Reset Circuitry 19922 - 3 READ CYCLE DATA IN ADDRESS ...
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FLAG_MAP 66 GND VDD S 69 SDO 70 SDO 71 GND S 72 VBLANKS/L VBLANKS/L 73 BYPASS_EDH 74 SDOMODE 75 BLANK_EN 76 ANC_CHKSM 77 CLIP_TRS 78 ...
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... SS2 C19 100pF C20 C21 100n 10n C23 C24 C22 100n 100n 3p3 C26 R31 1k8 15n Fig. 18 GS9025A - GS9020A - GS9028 Schematic Diagram (advanced operation schematic) 19922 - 3 USER SELECTED OPTIONS C40 10n 2 GND 3 GND ...
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... P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. 13˚ TYP ±0.20 16.00 ± ...