GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 33

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GS4910B

Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
Table 2-2: AC Electrical Characteristics (Continued)
V
Parameter
Digital Timing Output Rise/Fall
Times
15pF load
20% - 80%
GSPI
GSPI Input Clock Frequency
GSPI Clock Duty Cycle
GSPI Input Setup Time
GSPI Input Hold Time
NOTES
1. The video output clock may be directly connected to Gennum’s GS1532 or GS1531 serializer for a SMPTE-compliant SDI or HD-SDI
2. All SD standards EXCEPT VID_STD[5:0] = 1 (450ps typ.) and VID_STD[5:0] = 5 or 6 (500ps typ.)
3. All HD and Graphics standards EXCEPT VID_STD[5:0] = 22 (300ps typ.) and VID_STD[5:0] = 41-43 (400ps typ.)
4. Timings from any CLK output to any other CLK output.
5. If fs=96kHz and ACLK is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typically have a 33% duty cycle distortion.
6. With PCLK phasing delay set to nominal (zero offset), each increment of the clock phasing adjustment decreases output hold time and
7. For detailed GSPI timing parameters, please refer to
DD
output with output jitter below 0.2UI, when the serializer is configured for a loop bandwidth of 100KHz.
See
delay time by a nominal 700ps. The times t
= 1.8V, T
Section 3.7.2 on page
A
= 0°C to 70°C, unless otherwise specified.
63.
Symbol
f
DC
t
t
GSPI
3
8
36655 - 2
in
in
GSPI
Figure 3-18
Figure 3-18
OD
and t
OH
April 2006
Table
Condition
IO_VDD = 1.8V
current drive = LOW
IO_VDD = 3.3V
current drive = LOW
IO_VDD = 1.8V
current drive =
HIGH
IO_VDD = 3.3V
current drive =
HIGH
are defined in
3-12.
Figure
2-1.
Min
1.5
1.5
40
GS4911B/GS4910B Data Sheet
Typ
Max
10.0
3.0
1.5
2.5
1.4
60
Units
MHz
ns
ns
ns
ns
ns
ns
%
33 of 113
Notes
7
7
7
7

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