GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 83

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

Table 3-13: Configuration and Status Registers (Continued)
Register Name
Output_FV_Reset
Frame_Divider_Reset
Address
18h
19h
19h
19h
36655 - 2
15-0
Bit
15-2
1
0
April 2006
When the output is genlocked to the input, the input
Description
reference is used to reset the frame-based counter
controlling the generated timing output signals.
Programming this register to a non-zero value will
over-ride the internal frame-based counter. The counter
reset will occur every Output_FV_Reset input frames.
This register is programmed when manually
programming the internal video genlock block.
NOTE: Once this register is programmed, it must be
updated using register 19h.
The default value of this register will vary depending on
the output video standard selected.
Reference:
Reserved. Set these bits to zero when writing to 19h.
Ref_F_Sync - when Ref_F_Mode (bit 0 of 19h) is set
HIGH, this bit is used to initialize the frame-based
counter reset programmed in 18h.
The reset pulse is generated if this bit is pulsed (LOW to
HIGH to LOW) during the output frame immediately
prior to the frame the reset is to occur.
This register is programmed when manually
programming the internal video genlock block.
Reference:
Ref_F_Mode - set this bit HIGH to initialize the
frame-based reset via the host interface (using bit 1
above).
Reference:
Section 3.6.2 on page 54
Section 3.6.2 on page 54
Section 3.6.2 on page 54
GS4911B/GS4910B Data Sheet
R/W
R/W
–
R/W
R/W
Default
–
–
0
0
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