GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 40

• Manufacturer Part Number: GS4910B
• Description: HD/SD/Graphics Clock and Timing Generator with GENLOCK
• Manufacturer: GENNUM [Gennum Corporation]

3.2.1.2 Freeze Mode
3.2.2 Free Run Mode
4. For sync-based input references, the device will advance all line-based output
5. For blanking-based input references, the device will advance all line-based
6. The offsets that occur as described in notes 1-5 are independent of one
When the device is in Genlock mode and the input reference is removed, the
GS4911B/GS4910B will enter Freeze mode. The behaviour of the device during
loss and re-acquisition of an input reference signal is described in
page
In Freeze mode, the frequency of the output clock and timing signals will be
maintained to within +/- 2ppm. This assumes a loop bandwidth of 10Hz. Also, if the
frequency of the 27MHz reference crystal shifts while in Freeze mode, the
frequency of the output clock and timing signals will shift as well.
The GS4911B/GS4910B will enter Free Run mode when the GENLOCK pin is set
HIGH by the application layer. In this mode, the occurrence of all frequencies is
based on the external 27MHz reference input. Therefore, the frequency of the
output clock and timing signals will have the same accuracy as the crystal
reference.
If operating in Free Run mode, using a more accurate crystal (e.g. 10ppm) ensures
more accurate clock and timing signals are generated.
NOTE: In Free Run mode, the audio clocks of the GS4911B will remain genlocked
to the video clock.
36655 - 2
timing signals by 1 line if the value programmed in the H_Offset register is
greater than 20. The user may compensate for this advance by adding 1 line
to the desired vertical offset before loading this value into the register. In
addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of
register 16h will be LOW when H_Offset = 21 only, although the device will
remained genlocked. The user may choose to mask these lock signals such
that the device will continue to report genlock under this condition.
output timing signals by 1 line if the value programmed in the H_Offset register
is greater than the number of output video clock cycles from the start of H
Sync to the end of active video (Hsync_to_EAV) + 20. The value of
Hsync_to_EAV is reported in register 51h and changes according to the output
VID_STD selected. The user may compensate for this advance by adding 1
line to the desired vertical offset before loading this value into the register. In
addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of
register 16h will be LOW when H_Offset = Hsync_to_EAV + 21 only, although
the device will remained genlocked. The user may choose to mask these lock
signals such that the device will continue to report genlock under this
condition.
another and must be accounted for as such.
47.
April 2006
GS4911B/GS4910B Data Sheet
Section 3.5.3 on
40 of 113