GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet
GS4910B
Related parts for GS4910B
GS4910B Summary of contents
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... It can be used to generate video and audio clocks and timing signals, and allows multiple devices to be genlocked to an input reference. The GS4910B includes all the features of the GS4911B, but does not offer audio clocks or AFS pulse generation. The GS4911B/GS4910B will recognize input reference ...
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... Flywheel and Video Timing Generator Clock Synthesis and Control Clock pclk Phase Adjust aclk_512 aclk_384 Application Programming Interace GS4911B Functional Block Diagram 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet user[4:1] AFS 10FID DE F digital Crosspoint F sync V blanking V sync H blanking H sync Video Clock 3x Video Clock ...
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... VSYNC FSYNC 10FID 27MHz ref_rate Flywheel and Video Timing Generator Clock Synthesis and Control Clock pclk Phase Adjust Application Programming Interace GS4910B Functional Block Diagram 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet user[4:1] 10FID DE F digital F sync Crosspoint V blanking V sync H blanking H sync ...
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... Contents Key Features .................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................8 1.1 GS4911B Pin Assignment ..............................................................................8 1.2 GS4910B Pin Assignment ..............................................................................9 1.3 Pin Descriptions ............................................................................................10 1.4 Pre-Programmed Recognized Video and Graphics Standards ....................20 1.5 Output Timing Signals ...................................................................................25 2. Electrical Characteristics .........................................................................................29 2.1 Absolute Maximum Ratings ..........................................................................29 2.2 DC Electrical Characteristics ........................................................................29 2.3 AC Electrical Characteristics .........................................................................31 2.4 Solder Reflow Profiles ...................................................................................35 3. Detailed Description ................................................................................................36 3 ...
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... Device Power-Up ......................................................................................106 3.14.1 Power Supply Sequencing...............................................................106 3.15 Device Reset .............................................................................................106 4. Application Reference Design ...............................................................................107 4.1 GS4911B Typical Application Circuit ..........................................................107 4.2 GS4910B Typical Application Circuit ..........................................................108 5. References & Relevant Standards ........................................................................109 6. Package & Ordering Information ...........................................................................110 6.1 Package Dimensions ..................................................................................110 6.2 Recommended PCB Footprint ....................................................................111 6 ...
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... List of Figures GS4911B Functional Block Diagram........................................................................... 2 GS4910B Functional Block Diagram........................................................................... 3 Figure 1-1: XTAL1 and XTAL2 Reference Circuits ....................................................19 Figure 2-1: PCLK to TIMING_OUT Signal Output Timing ..........................................34 Figure 2-2: Maximum Pb-free Solder Reflow Profile (preferred) ................................35 Figure 2-3: Standard Pb Solder Reflow Profile .........................................................35 Figure 3-1: HD-SD Calculation ...................................................................................39 Figure 3-2: Output Accuracy and Modes of Operation ...............................................41 Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a Sync Separator ...
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... Table 3-8: Audio Clock Divider................................................................................... 64 Table 3-9: Encoding Scheme for AFS_Reset_Window ............................................. 65 Table 3-10: Audio Sampling Frequency to Video Frame Rate Synchronization ........ 66 Table 3-11: Crosspoint Select .................................................................................... 71 Table 3-12: GSPI Timing Parameters ........................................................................ 78 Table 3-13: Configuration and Status Registers ........................................................ 79 Table 5-1: References & Relevant Standards.......................................................... 109 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 7 of 113 ...
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... X1 6 GS4911B X2 7 64-pin QFN 8 (Top View 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet LVDS/PCLK3_GND 48 PCLK3 47 PCLK3 46 LVDS/PCLK3_VDD 45 CORE_VDD 44 TIMING_OUT_8 43 TIMING_OUT_7 42 TIMING_OUT_6 41 TIMING_OUT_5 40 TIMING_OUT_4 ...
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... GS4910B Pin Assignment LOCK_LOST REF_LOST VID_PLL_VDD VID_PLL_GND XTAL_VDD XTAL_GND CORE_GND ANALOG_VDD ANALOG_GND ANALOG_GND ANALOG_GND 10FID HSYNC Ground Pad (bottom of package GS4910B X2 7 64-pin QFN 8 (Top View ...
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... The input reference applied does not meet the minimum/maximum timing requirements described in This pin will be LOW otherwise. If the reference signal is removed when the device is in Genlock mode, REF_LOST will go HIGH and the GS4911B/GS4910B will enter Freeze mode (see – Power ...
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... Synchronous Signal levels are LVCMOS/LVTTL compatible. The VSYNC external reference signal is applied to this pin by the application layer. When the GS4911B/GS4910B is operating in Genlock mode, the device senses the polarity of the VSYNC input automatically, and references to the leading edge. If the user wishes to select one of the pre-programmed video and/or ...
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... The FSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. on page 20 recognized by the GS4911B/GS4910B. For blanking-based references, the FSYNC signal should be set HIGH during the second field. NOTE: If the input reference format does not include an F sync signal, this pin should be held LOW ...
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... The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Table 3-7. for signal descriptions 113 ...
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... The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet for signal descriptions. for signal descriptions. for signal descriptions. for signal descriptions 113 ...
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... This signal will be high impedance when VID_STD[5:0] = 00h. – Power Most positive power supply connection for PCLK3 output circuitry and Supply LVDS driver. Connect to +1.8V DC. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet for signal descriptions. for signal descriptions. for signal descriptions 113 ...
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... By default, the current drive will be low. It must be set high if the clock rate is greater than 100MHz. The PCLK2 output will be held LOW when VID_STD[5:0] = 00h. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet present a differential video sample rate clock output to outputs by programming designated registers in the PCLK3 / ...
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... All JTAG / Host Interface address and data are shifted into/out of the device synchronously with this clock. Host Mode (JTAG/HOST = LOW): SCLK_TCLK operates as the host interface serial data clock, SCLK. JTAG Test Mode (JTAG/HOST = HIGH): SCLK_TCLK operates as the JTAG test clock, TCLK. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 17 of 113 ...
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... When asserted LOW, all host registers and functional blocks will be set to their default conditions and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence will resume. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 18 of 113 ...
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... Capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance serves as an input, which may alternatively accept a 27MHz clock source. To accomodate this, mismatched capacitor values are recommended. Figure 1-1: XTAL1 and XTAL2 Reference Circuits 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 6 X1 clock ...
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... Pre-Programmed Recognized Video and Graphics Standards Table 1-2 describes the video and graphics standards automatically recognized by the GS4911B/GS4910B. Any one of the 36 different video formats and 16 different graphic display formats listed below can be applied to the GS4911B/GS4910B and automatically detected by the reference format detector. Moreover, each format, with the exception of VID_STD[5: 52, 53, or 54, is available for output on the timing output pins by setting the VID_STD[5:0] pins ...
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... Section 3.10 on page The width of the H Sync output pulse is determined by the selected video standard. video and graphics standard recognized by the GS4911B/GS4910B. Custom video timing parameters may also be programmed in the host interface to define a unique H Sync width (see In Genlock mode the leading edge of the output H Sync signal is nominally simultaneous with the half amplitude point of the reference HSYNC input ...
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... The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see 74). Section 3.10 on page 74). Table 1-2), or according to custom V Sync 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Default Output Pin TIMING_OUT_3 Table 1-2), Section 3.2.1.1 on Section 3.12.3 on TIMING_OUT_4 Section 3.2.1.1 on Section 3.12.3 on page 79). ...
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... HIGH (default 67). Section 3.8.1 on page 67 for more detail on the 10FID output signal. Table 1-2), or according to custom timing 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Default Output Pin TIMING_OUT_6 Section 3.10 on page 74). Section 3.2.1.1 on Section 3.12.3 on page 79). TIMING_OUT_7 Section 3 ...
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... Please see USER_1~4 The GS4911B/GS4910B offers four user programmable output signals. Each USER signal is controlled by four timing registers and a polarity select bit. The timing registers define the start and stop times in H pixels and V lines and begin ...
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... IO_VDD 1.8V Operation IO_VDD 3.3V Operation VID_PLL_VDD – AUD_PLL_VDD – ANALOG_VDD – XTAL_VDD 1.8V Operation XTAL_VDD 3.3V Operation PhS_VDD – 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Conditions Value/Units – -0.3V to +2.1V – -0.3V to +3.6V IO_VDD = +3.3V -0.3V to +5.5V IO_VDD = +1.8V -0.3V to +3.6V – -20°C < T < 85°C A – -50°C < T STG – 260°C – ...
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... LOW as selected – IO_VDD = 1.8V current drive = LOW – IO_VDD = 3.3V current drive = LOW – IO_VDD = 1.8V current drive = HIGH – IO_VDD = 3.3V current drive = HIGH 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Min Typ Max Units – – 450 mW – 300 – mW – – 400 mW – ...
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... OCM V – ODIFF – To 1.8V or GND Condition from when the reference input is first present – SD video standards XTAL_VDD = 3.3V HD & Graphics video standards XTAL_VDD = 3.3V – 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Min Typ Max Units – 5 – mA – 7 – mA – 7 – mA – 14 – ...
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... IO_VDD = 1.8V current drive = LOW IO_VDD = 3.3V current drive = LOW IO_VDD = 1.8V current drive = HIGH IO_VDD = 3.3V current drive = HIGH – – OD – OH 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Min Typ Max Units – – 1.7 – – 1.5 – – 1.1 – – 0.9 – – ...
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... IO_VDD = 3.3V current drive = HIGH – GSPI – GSPI in Figure 3-18 – Figure 3-18 – 8 and t are defined in Figure OD OH Table 3-12. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Min Typ Max – – 3.0 – – 1.5 – – 2.5 – – 1.4 – – 10.0 40 – 60 1.5 – – ...
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... Free Run mode, the output clock and timing signals will have the same accuracy as the crystal. However, if operating in Genlock mode, all output signals are based on the input reference, and therefore a less accurate crystal may be sufficient. See 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet ...
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... Figure 2-3: Standard Pb Solder Reflow Profile 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Figure Figure 2-3. 60-150 sec. 20-40 sec. 3˚C/sec max 8 min. max 60-150 sec. 10-20 sec. 3˚C/sec max 6 min ...
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... The GS4911B/GS4910B will operate in either Genlock mode or Free Run mode depending on the setting of the GENLOCK pin. These two modes are described in Section 3.2.1 on page 37 and Section 3 ...
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... Genlock timing offsets can be used to co-time the output of a piece of equipment containing the GS4911B/GS4910B with the outputs of other equipment at different locations. The signal leaving the piece of equipment containing the GS4911B/GS4910B may pass through processing equipment with significant fixed delays before arriving at the switcher ...
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... HSYNC reference. This will occur even when the H_Offset register is not programmed. The user may compensate for this delay by subtracting 2 PCLK cycles from the desired horizontal offset before loading the value into the host interface. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Bits Required to Clock_Phase_Offset Set the Number [15:0] Settings of Steps ...
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... H_Feedback_Divide represents the numerator of the ratio of the output clock frequency to the frequency of the H reference pulse calculated as described in Section 3.6.2.1 on page HSYNC Δ VSYNC_HSYNC VSYNC H Sync V Sync Δ VSync Figure 3-1: HD-SD Calculation 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Δ VSYNC _HSYNC 2 ( × HSYNC_OUT_Period + – 54. HSYNC_IN_Period HSync_OUT_Period ) 39 of 113 ...
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... Freeze mode, the frequency of the output clock and timing signals will shift as well. The GS4911B/GS4910B will enter Free Run mode when the GENLOCK pin is set HIGH by the application layer. In this mode, the occurrence of all frequencies is based on the external 27MHz reference input ...
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... MHz -100ppm - t Free Run Genlock No Input Reference Reference Applied NOTES represents the temperature variability of the crystal 2. Diagram not to scale. Figure 3-2: Output Accuracy and Modes of Operation 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet + t +2ppm -2ppm - t Freeze Time Reference Lost 41 of 113 ...
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... Genlock mode if GENLOCK = LOW. When operating in Free Run or Genlock mode, the GS4911B/GS4910B will continuously monitor the settings of the VID_STD[5:0] and ASR_SEL[2:0] pins. If the user wishes to change the format of the output clocks and timing signals, these pins may be reconfigured at any time, although it is recommended that the device be reset when changing output video standards ...
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... Typical H Timing Alternative H Timing The HSYNC, VSYNC, FSYNC, and 10FID reference signals are applied to the GS4911B/GS4910B via the designated input pins. To operate in Genlock mode, the input reference signals must be valid and must conform to a recognized video or graphics standard (see Alternatively, if VID_STD[5:0] = 62, the signal applied to the HSYNC input must be stable and have a period of less than 2 ...
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... Timing for Graphics Formats The GS4911B/GS4910B is pre-programmed to recognize the timing for 16 different graphics formats presented to the input reference pins. These graphic formats are described in Section 1.4 on page The supported graphics standards are all progressive, and do not use the FSYNC signal. Therefore, FSYNC should be held LOW by the application layer. The VESA formats supported have a 0 ...
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... Input Reference Validity To accommodate any standards that employ the polarity of the H and V sync signals to indicate the format of the display, the GS4911B/GS4910B will recognize H and V sync polarity and automatically synchronize to the leading edge. The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the Video_Status register ...
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... The REF_LOST output pin may also be read via bit 0 of the Genlock_Status register (see Section 3.12.3 on page There are some standards with identical H, V, and F timing parameters, such that the GS4911B/GS4910B’s reference format detector cannot distinguish between them. Table 3-2 groups standards with shared H, V, and F periods. Using the Amb_Std_Sel register at address 10h of the host interface, the user may select their choice of standard to be identified with a particular set of measurements ...
Page 47
... By default, the GS4911B/GS4910B will ignore one missing H pulse on the HSYNC pin and will continue to operate in Genlock mode (although the LOCK_LOST pin will temporarily be set HIGH). This behaviour is controlled by the Run_Window bits of register address 24h. If there are two consecutive missing H pulses on the HSYNC input pin, the REF_LOST and LOCK_LOST pins will both go HIGH and the device will enter Freeze mode ...
Page 48
... Re-write the value read in step 1 to register address 24h. This procedure will force the device to lock to the reference as described above, but will maintain the flywheeling capability of the GS4911B/GS4910B should a single missing H pulse occur in the genlocked state. To avoid the above procedure, the user may choose to clear the Run_Window bits [2:0] of register address 24h upon power-up or reset ...
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... The maximum allowable frequency drift is measured as a fraction of the frequency of the reference H pulse. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Table 3-3. The default value of the register is Bh. Register Maximum Allowable Setting Frequency Drift Section 3 ...
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... This automatic locking process is described in page 50. If the output format selected is such that it is not commonly genlocked to the input reference, the GS4911B/GS4910B will not automatically lock. In this case, the user may program designated registers to manually allow locking to occur. The manual locking process is described in ...
Page 51
... It will then lock the output format to the reference, adjust the output timing parameters based on the genlock timing offset registers LOCK_LOST pin LOW. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 54). Section 3.12.3 on page 79. 74). It has the additional feature of (Section 3.2.1.1 on page ...
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... Manual Locking Process 3.6.2.1 Programming the Internal Video Genlock Block and Output Line/Frame Reset Registers Using the host interface, the GS4911B/GS4910B may be manually programmed to genlock certain video formats and audio clocks that are not automatically genlocked by the device. The following sections discuss when the user should manually program the internal video and/or audio genlock block, and how these blocks are programmed ...
Page 55
... Input Frame Rate 600 Therefore, program Output_FV_Reset = 600. The numerator does not have to be programmed. Additionally, the Frame_Divider_Reset register (address19h) must be configured to initialize the counter reset programmed in register 18h. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 1716 127413 4719 × ----------- - ----------------- - 74.25 ...
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... A simplified version of the GS4911B’s internal audio genlock block is shown in Figure 3-7. Internal Audio Genlock Block Output Video Clock A_Reference_Divide ( ( f out (host address 3Dh - 3Eh) Figure 3-7: Internal Audio Genlock Block 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 27000000 ----------------------- - = 1716 74250000 1000 × ----------------------- - ----------- - = 1650 1001 × ...
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... A_Reference_Divide 27000000 Therefore, program A_Feedback_Divide = 1792 and A_Reference_Divide = 1125. Note that n=1024 when programming a custom audio clock (see page 73). 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet out Table 3-5. Value of constant (n) X 3072 YES 1024 NO 1536 43008 1792 -------------- - ----------- - ...
Page 58
... Section 3.5.3 on page the reference is removed and subsequently re-applied during Genlock mode. The default loop bandwidth of the GS4911B/GS4910B's internal video PLL is 10Hz when the output video standard is the same as the input reference format. For other cross-locking combinations, the default loop bandwidth may be smaller than 1Hz or as large as 30Hz ...
Page 59
... NOTE: The value programmed in the Video_Res_Genlock register must be between 32 and 42. The value programmed in the Video_Cap_Genlock register must be greater than 10. These limits define the exact range of loop bandwidth adjustment available. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Section 3.6.2.1 on page 1716 ----------- - 1 9 – × ...
Page 60
... When locking to an SDI input, the user should consider the possibility of a switch of the SDI signal upstream from the system. If the GS4911B/GS4910B is locked to the digital H, V, and F blanking signals produced by a deserializer, and the SDI input to the deserializer is switched such that the phase of the H input changes abruptly, the REF_LOST output will remain LOW and the GS4911B/GS4910B will not crash lock to the new H phase ...
Page 61
... VSYNC and output V Sync signals occurring each time a switch in the SDI stream causes an abrupt phase change of the H input to the GS4911B/GS4910B. This will only occur when attempting to lock the "f/1.001" HD output standards to the 525-line SD input references standards, or vice versa ...
Page 62
... H Sync timing signal either on its rising or falling edge. The PCLK1 to PCLK3 outputs may also be individually delayed with respect to the eight TIMING_OUT signals to allow for skew control downstream from the GS4911B/GS4910B. Using the PCLK_Phase/Divide registers, the phase of each clock may be delayed nominal 10.3ns in 16 steps of approximately 700ps each (Table 3-6) ...
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... The z bit will go HIGH for one fs period every 192 fs periods. Its phase is not defined by any timing event in the GS4911B, and so is arbitrary. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 72). Section 3.12.3 on page Sampling Frequency (kHz) Audio Clock Generation Disabled 32 44 ...
Page 64
... AFS_Reset_Window may be set as desired. See NOTE: To maintain correct audio clock frequencies for some VESA standards, the window tolerance shown in Table 3-9 setting. In this case, set the AFS_Reset_Window register to 1XX. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Audio Clock Frequency fs 64fs 128fs 192fs* 256fs ...
Page 65
... H sync input of line 1 on every fifth frame (+/- the allowable drift specified in Table 3-9). The number of audio sample clocks during a video frame is shown in for 32, 44.1, and 48kHz audio sampling frequencies. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet kHz (enable_384fs = 1) 0.030 0.030 0.057 0.057 0.112 ...
Page 66
... To disable the signal on the external 10FID pin from resetting the AFS output pulse, set bit 0 of the Audio_Control register HIGH. If using the host interface to reset the 10FID pulse, the external 10FID pin must be grounded. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 30fps 50fps 59.94fps 3200/3 640 8008/15 ...
Page 67
... Additional information pertaining to the 10FID, AFS, and USER_1~4 signals can be found in the sub-sections below. When the GS4911B/GS4910B is operating in Genlock mode, the H, V, and F based output timing signals are synchronized to the H, V, and F reference signals applied to the inputs by the application layer. The video timing outputs may be ...
Page 68
... LOW on the leading edge of the H Sync pulse of line 1 of the second field in the sequence. The AFS timing in this configuration is similar to the 10FID optional timing shown in 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Total Field Section 3.12 frame in the sequence, and therefore identifies Figure 3-10 ...
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... As described in Table 1-3, the GS4911B/GS4910B offers 4 user programmable output signals which are available independent of the selected output video format. Each user signal is individually programmable and the polarity, position, and width of each output may be defined with respect to the digital output timingof the device. ...
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... See V_Start V_Stop AND=0, OR=0, XOR=0 (default) V_Start V_Stop AND=0, OR=1 Shading indicates when USER_x signal is active Figure 3-11: USER Programmable Output Signal 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Section 3.12.3 on page 79. V_Start V_Stop AND=1 V_Start V_Stop AND=0, OR=0, XOR 113 ...
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... GS4911B. The bit setting 1010b will be ignored by the GS4910B. The current-drive of each timing output pin is also selectable via the Output_Select registers. The current drive of each TIMING_OUT pin is low by default. However, it may be set high to accommodate certain applications. ...
Page 72
... In addition to the device’s pre-programmed clock frequencies, the user may generate a custom audio or video clock by programming designated registers in the host interface. Custom video clock generation is supported by both the GS4910B and GS4911B and is described in Section 3.9.1 on page only supported by the GS4911B and is described in The fundamental frequency of the video clock is defined by the output video format initially set by VID_STD[5:0] ...
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... Using registers 3Fh to 41h, the custom audio sampling frequency generated may then be multiplied by a factor of 64, 128, 256, or 512 before being presented to the ACLK pins. NOTE: The AFS reset described in active. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet = 91 the equation ...
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... HSYNC. In this case the user is required to manually program the video genlock block (see page 54). 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Section 3.9.1 on page 72. Clocks_Per_Line (4Eh) Hsync_To_EAV (51h) Lines_Per_Field (52h) Vsync_To_Last_Active_Line (55h) 45, when VID_STD[5:0] = 62, the device will Section 3 ...
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... The embedded clock must be 48kHz. The 24kHz reference signals for each audio group must be applied to the HSYNC input pin of a GS4911B/GS4910B, while a divided version of this signal must be applied to the VSYNC input pin. The divided signal must meet the requirements for VSYNC validity given in Section 3 ...
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... CS2 SDIN Figure 3-14: GSPI Application Interface Connection All read or write access to the GS4911B/GS4910B is initiated and terminated by the host processor. Each access always begins with a 16-bit command word on SDIN indicating the address of the register of interest. This is followed by a 16-bit data word on SDIN in write mode 16-bit data word on SDOUT in read mode. ...
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... Auto-Increment bit and a 12-bit address. command word format and bit configurations. Command words are clocked into the GS4911B/GS4910B on the rising edge of the serial clock, SCLK, which operates in a burst fashion. When the Auto-Increment bit is set LOW, each command word must be followed by only one data word to ensure proper operation ...
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... Figure 3-17: GSPI Read Mode Timing D15 D14 D15 D14 Figure 3-18: GSPI Write Mode Timing 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet t 6 D14 D12 D11 D10 D13 D13 D12 D11 D10 D13 D12 ...
Page 79
... H_16_Period 0Bh V_Lines 0Ch V_2_Lines 0Dh F_Lines 0Eh Table 3-13 summarizes the GS4911B/GS4910B's internal status and configuration registers. All registers are available to the host via the GSPI and are all individually addressable. Bit Description – Reserved. 15-0 Contains the number of 27MHz pulses in the input H Sync period ...
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... Reference: Section 3.2.1.2 on page 40 11-6 Forced_Standard - When bit 12 is set HIGH, the GS4911B/GS4910B will use the value programmed in these bits, rather than the value in bits 5-0, to determine the input reference format. The 6-bit value programmed here should always correspond to the VID_STD[5:0] value of the applied reference. ...
Page 81
... Reference: Section 3.6.1 on page 50 0 Reference_Present - this bit will be HIGH when a valid input reference signal has been applied to the device. The REF_LOST output pin is an inverted copy of this bit. Reference: Section 3.5.2 on page 45 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R N/A R N/A R N/A ...
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... Reference_Lock (bit 5 of register 15h). Reference: Section 3.6.1 on page 50 2 H_Lock_Mask - if this bit is set HIGH, the GS4911B/GS4910B will ignore the status of H_Lock (bit 2 of register 15h) when determining the status of Reference_Lock (bit 5 of register 15h). Reference: Section 3.6.1 on page 50 1 ...
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... Reference: Section 3.6.2 on page 54 0 Ref_F_Mode - set this bit HIGH to initialize the frame-based reset via the host interface (using bit 1 above). Reference: Section 3.6.2 on page 54 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – – – R 113 ...
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... Reserved. Set these bits to zero when writing to 1Ah. 3 AFS_Reset (GS4911B only) - set this bit HIGH to use Reset_Sync (bit 0 of register 1Ah) to reset the output AFS pulse. NOTE: This bit will remain LOW in the GS4910B. Set this bit LOW when writing to address 1Ah of the GS4910B. Reference: Section 3.7.2.1 on page 65 ...
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... A_pll_Lock (GS4911B only)- this bit will be HIGH when the generated audio clock is locked to the video clock reference. NOTE: This bit will remain high in the GS4910B. Reference: bit 1 of register 15h. 0 V_pll_Lock - this bit will be HIGH when the generated video clock is locked to the H Sync input reference. ...
Page 86
... NOTE: Once this register is programmed, it must be updated using bit 6 of register 16h. The default value of this register will vary depending on the output video standard selected. Address 22h = bits 15-0 Address 23h = bits 31-16 Reference: Section 3.9.1 on page 72 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – R/W – 113 ...
Page 87
... Control signal to adjust loop bandwidth of video genlock block. The value programmed in this register must be between 32 and 42. The default value of this register will vary depending on the output video standard selected. Reference: Section 3.6.4 on page 58 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – R/W – R/W – – ...
Page 88
... Section 3.7.1 on page 61 0 Divide_By_2 - set this bit HIGH to divide the output PCLK1 by two. NOTE: Setting this bit and bit 1 simultaneously HIGH will hold the PCLK1 pin LOW. Reference: Section 3.7.1 on page 61 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – R/W – – – R/W ...
Page 89
... PCLK3 / PCLK3 pins. Reference: Section 3.7.1 on page 61 15-2 Reserved. Set these bits to zero when writing to 2Fh. 1-0 Set these bits to 11b to tristate the PCLK3 / PCLK3 pins. Reference: Section 3.7.1 on page 61 – Reserved. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 0 R/W 0 R/W 0 R/W 0 – ...
Page 90
... Reserved. Set these bits to zero when writing to 32h. 2-0 Replaces the external ASR_SEL[2:0] pins when Host_ASR_Select (bit 2 of address 31h) is HIGH. The default setting of this register corresponds to an audio sample rate of 48kHz. Reference: Section 3.7.2 on page 63 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 010b Table 3-9. R/W ...
Page 91
... This register may be programmed to manually genlock the audio clock to the video clock. The default value of this register will vary depending on the output video standard selected. Address 3Bh = bits 15-0 Address 3Ch = bits 31-16 Reference: Section 3.6.2.2 on page 56 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – 73. R/W – 73. – ...
Page 92
... See NOTE: To output a frequency of 348fs or 192fs, bit 5 of register 31h must also be set HIGH. Reference: Section 3.7.2 on page 63 – Reserved. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W R/W – R/W Table 3-8 for more details. – R/W Table 3-8 for more details. – ...
Page 93
... TIMING_OUT_4 pin. See Table 3-11 for more details. Note: The default setting of this register is 0100b, which corresponds to V Blanking. Reference: Section 3.8.4 on page 71 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 0 R/W 0001b – ...
Page 94
... TIMING_OUT_8 pin. See Table 3-11 for more details. Note: The default setting of this register is 1000b, which corresponds to Display Enable (DE). Reference: Section 3.8.4 on page 71 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 0 R/W 0101b – ...
Page 95
... H Sync to the end of active video for the selected output timing format. If VID_STD[5:0] = 62, this register may be set by the user when programming custom output timing signals. Otherwise, this register is read-only. Reference: Section 3.10 on page 74 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – – – R/W 0 – ...
Page 96
... NOTE: The user cannot specify a custom vertical blanking signal to end in the middle of a line. If this occurs, the device will automatically adjust the timing of the signal to fall at the beginning of the next line. Reference: Section 3.10 on page 74 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W – R/W – R/W – ...
Page 97
... By default, the AFS signal is HIGH for the duration of the first line of the n’th video frame to indicate that the ACLK dividers have been reset at the start of line 1 of that frame. NOTE: The GS4910B does not generate an AFS pulse and will ignore the setting of this bit. Reference: Table 1-3 ...
Page 98
... V Sync signal USER1_V. For interlaced output standards, this value corresponds to the odd field number. NOTE: The value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. Reference: Section 3.8.3 on page 69 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W 0 R/W 0 R/W 0 R/W ...
Page 99
... V Sync signal USER2_V. For interlaced output standards, this value corresponds to the odd field line number. NOTE: The value programmed in this register must be less than the value programmed in V_Stop_2. Reference: Section 3.8.3 on page 69 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 1 R/W 0 ...
Page 100
... H Sync signal USER3_H. NOTE: The value programmed in this register must not exceed the maximum number of clock periods per line of the outgoing standard. Reference: Section 3.8.3 on page 69 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 0 – – ...
Page 101
... Set this bit HIGH to output a signal with the following attributes: Signal becomes active when either USER3_H or USER3_V is active. Signal is inactive when USER3_H and USER3_V are both active or both inactive. Reference: Section 3.8.3 on page 69 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 0 – – ...
Page 102
... V Sync signal USER4_V. For interlaced output standards, this value corresponds to the odd field line number. NOTE: The value programmed in this register must not exceed the maximum number of lines per field of the outgoing standard. Reference: Section 3.8.3 on page 69 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default R/W 0 R/W 0 – – R/W 0 – ...
Page 103
... To fully enable this mode, VID_STD[5:0] must be set to 4d, and the F_Lock_Mask and V_Lock_Mask bits [4:3] of register address 16h must be set to 1. NOTE: Once this register is programmed, it must be updated using bit 6 of register 16h. Reference: Section 3.11 on page 75 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W Default – – R/W 1 R/W 0 ...
Page 104
... The device is locked to blanking signals from a deserializer, and the SDI input to the deserializer has been switched upstream from the system. See Section 3.6.5 on page 14-0 Reserved. Set these bits to zero when writing to 83h. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet R/W R/W Section 3.5.3 on 60. – Default 0 – ...
Page 105
... JTAG When the JTAG/HOST input pin of the GS4911B/GS4910B is set HIGH, the host interface port will be configured for JTAG test operation. In this mode, pins 57 through 60 become TCLK, TDI, TDO, and TMS. In addition, the RESET pin will operate as the test reset pin. Boundary scan testing using the JTAG interface will be enabled in this mode. ...
Page 106
... Device Reset Application HOST Tri-State Figure 3-20: System JTAG The GS4911B/GS4910B has a recommended power supply sequence. To ensure correct power-up, the ANALOG_VDD and CORE_VDD power pins should be powered before IO_VDD. Device pins may be driven prior to power-up without causing damage. In order to initialize operating conditions to their default states, the application layer must hold the RESET signal LOW during power up and for a minimum of 500us after the last supply has reached its operating voltage ...
Page 107
... AUD_PLL_VDD 15 10FID 16 HSYNC 65 GND_PAD VDD_IO 1V8_CORE 10n NOTE: For a solution with the lowest output jitter, the GS1531 or GS1532 serializers are recommended for use with the GS4911B/GS4910B. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet VDD_IO 10n 1V8_PCLK 10n 22R 22R Controlled impedance 100-ohms differential ...
Page 108
... HSYNC GND_A 65 GND_PAD VDD_IO 1V8_CORE 10n NOTE: For a solution with the lowest output jitter, the GS1531 or GS1532 serializers are recommended for use with the GS4911B/GS4910B. 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet VDD_IO 10n 1V8_PCLK 10n 22R 22R Controlled impedance 100-ohms differential ...
Page 109
... ITU-R BT.1358 Studio Parameters of 625 and 525 Line Progressive Scan Television Systems VESA Monitor Timing VESA and industry Standards and Guidelines for Computer Display Specifications Monitor Timing – Version 1.0, Revision 0.8 (Adoption Date: September 17, 1998) 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 109 of 113 ...
Page 110
... Package & Ordering Information 6.1 Package Dimensions PIN 1 AREA 2X 0. 0.15 C 0.10 C 64X 0.08 C SEATING PLANE A 9.00 B 4.50 C 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 7.10+/-0.15 3.55 CENTRE TAB 0.50 64X ALL DIMENSIONS IN MM +0.03 0.25-0.02 0. 0.05 C 110 of 113 ...
Page 111
... Parameter Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, θ Junction to Air Thermal Resistance, θ j-a Psi, ψ Pb-free and RoHS Compliant 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet 0.25 CENTER PAD 7.10 8.70 Value 9mm x 9mm 64-pin QFN 3 9.3°C/W j-c (at zero airflow) 24.6° ...
Page 112
... Graphics Clocks Clocks √ √ GS4911B √ √ GS4910B Part Number GS4911BCNE3 GS4910BCNE3 36655 - 2 April 2006 GS4911B/GS4910B Data Sheet Audio Full Clocks Programmability √ √ √ – Package Temperature Range Pb-free 64-pin QFN 0°C to 70°C Pb-free 64-pin QFN 0°C to 70°C ...
Page 113
... Corrected phrasing regarding user-programmable outputs. Added note on V Blanking output width for VID_STD= Corrected ESD protection to 1 kV. April 2006 Corrected description and formulas for loop bandwidth. Converted to Data Sheet. Clarified setting of VID_STD in Extended Audio Mode. Updated power consumption of GS4910B. 113 of 113 ...