GS4910B GENNUM [Gennum Corporation], GS4910B Datasheet - Page 49

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GS4910B

Manufacturer Part Number
GS4910B
Description
HD/SD/Graphics Clock and Timing Generator with GENLOCK
Manufacturer
GENNUM [Gennum Corporation]
Datasheet
3.5.4 Allowable Frequency Drift on the Reference
Acquisition of a New Reference
When a new reference is applied, the device continues to operate in Freeze mode
while the reference format detector checks for validity as described in
on page
Assuming GENLOCK is LOW, the device will then attempt to genlock the selected
output clock and timing signals to the new input reference. If the output can be
automatically genlocked to the new input reference, LOCK_LOST will go LOW and
the device will re-enter Genlock mode. Otherwise, the LOCK_LOST pin will remain
HIGH and the device will enter Free Run mode.
If VID_STD[5:0] = 63 when the new reference is applied, the device will send the
detected timing parameters to the clock synthesis and timing generator blocks. The
new output format will start being generated during the first reference V period after
the reference format has been reliably established. The LOCK_LOST pin will go
LOW and the device will re-enter Genlock mode.
By default, the frequency of the reference H pulse on HSYNC may drift from its
expected value by approximately +/- 0.2% before the internal video PLL loses lock.
This tolerance may be adjusted using the Max_Ref_Delta register at address 1Eh
of the host interface.
The encoding scheme is shown in
NOTE: Regardless of the setting of this register, the device will always differentiate
between 59.94Hz and 60Hz reference standards.
Table 3-3: Max_Ref_Delta Encoding Scheme
36655 - 2
The maximum allowable frequency drift is measured as a fraction of the frequency of the reference
H pulse.
Register
Setting
0h
1h
2h
3h
4h
5h
6h
7h
45. Once validity is detected, the REF_LOST pin is set LOW.
April 2006
Maximum Allowable
Frequency Drift
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
-20
-19
-18
-17
-16
-15
-14
-13
Table
3-3. The default value of the register is Bh.
GS4911B/GS4910B Data Sheet
Register
Setting
Ah
Bh
Ch
Dh
Eh
Fh
8h
9h
Maximum Allowable
Frequency Drift
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
+/- 2
Section 3.5.2
-12
-11
-10
-9
-8
-7
-6
-5
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