78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 6

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
input.
transmit clock from the serial plesiochronous data
and bypass the internal FIFO and re-timing block.
This mode is commonly used for mezzanine cards,
modules, and any application where the reference
clock cannot always be synchronous to the transmit
source clock/data.
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4 ÷ 4) or
38.88MHz (STM1 ÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data for both channels must be source
synchronous to the provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2352 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
*To
SMOD[1:0]=11
Page: 6 of 42
Parallel
Mode
Slave
Slave +
*Loop-timing
Master
Reference
Framer/
Mapper
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be re-
timed using the recovered receive clock
Clock
enable
In this mode, the 78P2352 will recover a
Figure 3: Plesiochronous; data only
(Tx CDR enabled, FIFO bypassed)
SDI_PAR
HW Control Pins
140 / 155 MHz
Loop-timing
High
High
High
NRZ
NRZ
CKMODE
SIxDP/N
SOxCKP/N
SOxDP/N
Float
High
Low
in
78P2352
CKREFP
TDK
software
SW Control Bits
CMIxP/N
XO
PAR
RXxP/N
1
1
1

CMI
CMI
2006 Teridian Semiconductor Corporation
mode
PMODE
XFMR
XFMR
0
0
1
set
Coax
Coax
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
specified limits, the FIFO will over or under flow, and
the FERRx register signal will be asserted.
signal can be used to trigger an interrupt.
interrupt event is automatically cleared when a FIFO
Reset (FRSTx) pulse is applied, and the FIFO is re-
centered.
Reference
Reference
Framer/
Mapper
Framer/
Mapper
Clock
Clock
Notes:
1) External remote loopbacks (i.e. loopback
2) Most E4 applications will not allow the use of
3) During IC power-up or transmit power-up,
within
synchronous
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2352 is configured for loop-timing.
the dual channel 78P2352 as each channel
is asynchronous to each other.
recommends using the single channel
78P2351 if one cannot control the E4 timing
reference for each channel.
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow.
manually reset using FRST anytime the
transmitter is powered-up.
4-bit CMOS TTL
4-bit CMOS TTL
4-bit CMOS TTL
4-bit CMOS TTL
Figure 5: Master Parallel Mode
34/39 MHz
34/39 MHz
34/39 MHz
34/39 MHz
Figure 4: Slave Parallel Mode
framer)
If the clock wander exceeds the
PIx[3:0]D
PIxCK
POx[3:0]D
POxCK
As such, the FIFO should be
PIx[3:0]D
PTOxCK
POx[3:0]D
POxCK
operation
OC-3/ STM1-E/ E4 LIU
CKREFP/N
78P2352
CKREFP/N
78P2352
TDK
TDK
are
CMIxP/N
CMIxP/N
RXxP/N
RXxP/N
not
Dual Channel
(FIFO
CMI
CMI
CMI
CMI
possible
78P2352
XFMR
XFMR
XFMR
XFMR
enabled)
Teridian
Rev. 2.4
Coax
Coax
Coax
Coax
This
This
in