78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 19

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

CONTROL PINS
Page: 19 of 42
NAME
FRST
LPBKx
CKMODE
PIN DESCRIPTION
17, 18
PIN
78
15
TYPE
(CONTINUED)
CIT
CIT
CIT
DESCRIPTION
FIFO Phase-Initialization Control:
When asserted, the transmit FIFO pointers are reset to the respective
“centered” states. Also resets the FIERR interrupt bit. De-assertion edge of
FRSTx will resume FIFO operation.
Because the internal VCO clock and off-chip transmit clocks may not be
stable during transmit power-up, it is recommended to always reset the FIFOs
after powering up the IC or the transmitter.
Not valid during Plesiochronous Serial Mode.
Analog Loopback Selection:
Clock Mode Selection:
Selects the method of inputting transmit data into the chip. See
TRANSMITTER OPERATION section for more information.
In PARALLEL mode (SDI_PAR high):
In SERIAL mode (SDI_PAR low):
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2006 Teridian Semiconductor Corporation
Low: Channel 1 FRST assertion
Float: Normal operation
High: Channel 2 FRST assertion
Low: Normal operation
Float: Remote Loopback Enable: Recovered receive data and clock
are looped back to the transmitter for retransmission.
High: Local Loopback Enable: The serial transmit data is looped back
and used as the input to the receiver.
Low: Parallel transmit clock is input to the 78P2352.
Float: Parallel transmit clock is input to the 78P2352. Loop-timing
High: Parallel transmit clock is output from the 78P2352
Low: Reference clock is synchronous to transmit clock and data.
Data is clocked in with SIxCKP/N and passed through a FIFO
Float: Reference clock is synchronous to transmit data. Clock is
recovered with a CDR and data is passed through a FIFO
High: Reference clock is plesiochronous to transmit data. Clock is
recovered with a CDR and the FIFO is bypassed
mode enabled.
OC-3/ STM1-E/ E4 LIU
Dual Channel
78P2352
Rev. 2.4