78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet
78P2352-IEL
Available stocks
Related parts for 78P2352-IEL
78P2352-IEL Summary of contents
Page 1
... NRZ to CMI conversion. The device can interface to 75Ω coaxial cable using CMI coding or directly to a fiber optics transceiver module using NRZ coding. 78P2352 is compliant with all respective ANSI, ITU- T, and Telcordia standards for jitter tolerance, generation, and transfer. APPLICATIONS • ...
Page 2
... ADDRESS N-4: MODE CONTROL REGISTER 2........................................................................14 ADDRESS N-5: STATUS MONITOR REGISTER ........................................................................15 PIN DESCRIPTION ....................................................................................................... 16 LEGEND ...............................................................................................................................................16 TRANSMITTER PINS ...........................................................................................................................16 RECEIVER PINS ..................................................................................................................................17 REFERENCE AND STATUS PINS ......................................................................................................18 CONTROL PINS ..................................................................................................................................19 SERIAL-PORT PINS ............................................................................................................................21 POWER AND GROUND PINS .............................................................................................................21 Page 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 3
... RECEIVER JITTER TOLERANCE ..........................................................................................................35 RECEIVER JITTER TRANSFER FUNCTION .........................................................................................37 CMI MODE LOSS OF SIGNAL CONDITION ..........................................................................................38 APPLICATION INFORMATION .................................................................................... 38 EXTERNAL COMPONENTS ...................................................................................................................38 (CMI) TRANSFORMER SPECIFICATIONS............................................................................................38 THERMAL INFORMATION .....................................................................................................................38 MECHANICAL SPECIFICATIONS ............................................................................... 39 PACKAGE INFORMATION (pinout)................................................................................................ ORDERING INFORMATION ......................................................................................... 41 Revision History ........................................................................................................................................42 Page 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU 41 Rev. 2.4 ...
Page 4
... See TRANSMITTER OPERATION section for more info. REFERENCE CLOCK The 78P2352 requires a reference clock supplied to the CKREFP/N pins. This reference clock is used for clock recovery in the Rx DLL and Tx DLL also used for transmit re-timing in the synchronous transmit modes ...
Page 5
... Figure 1: Synchronous clock and data available (Tx CDR bypassed, FIFO enabled off-chip serial transmit clock is not available Figure 2, the 78P2352 can recover a Tx clock from the serial NRZ data input and pass the data through the clock decoupling FIFO. The data is then re-clocked or re-timed using a clean synthesized clock generated from the provided reference clock ...
Page 6
... For maximum compatibility with legacy ASICs, the 78P2352 can operate in both slave and master clock modes as shown in Figures 4 and 5 respectively. Note: A loop-timing mode is also available to allow external remote loopbacks (i.e. line loopback in framer) ...
Page 7
... Low 1 Float 0 Transmit Loss of Lock In transmit modes using the integrated CDR, the 78P2352 will declare a loss of lock condition when there is no valid signal detected at the SIxDP/N data inputs. Note: The Tx LOL indicator is invalid and undefined when the parallel (nibble) interface is selected. ...
Page 8
... In SW mode only, a Full Remote (digital) Loopback bit FLBK is also available in the Advanced Tx Control register. This loopback exercises the entire Rx and Tx paths of the 78P2352 including the Tx clock recovery unit. As such, the user must enable either Serial Plesiochronous or Serial Loop-timing transmit modes to utilize the Full Remote (digital) Loopback ...
Page 9
... CMI -- -- -- <1> <X> <X> <0> RXLOS <X> <X> <X> <X> 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Bit 2 Bit 1 Bit 0 Read/ Sub-Address Write SA[1] SA[0] R/W* Bit 3 Bit 2 Bit 1 CKSL[ <X> <X> <X> MTLOL <0> <X> <1> <X> <X> <X> Bit 3 Bit 2 Bit 1 SMOD[0] MON -- < ...
Page 10
... Secondary values correspond to E4 frequencies. Default values depend on the CKSL pin selection upon reset. Reserved. Register Soft-Reset: When this bit is set, all registers are reset to their default values. This register bit is self-clearing. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 11
... Gates the TXLOL register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass FIERR Error Mask (active low): Gates the respective FIERR register bit to the INTTXxB interrupt pin. 0: Mask 1: Pass DESCRIPTION Reserved. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 12
... SMOD[1:0] default = 11 (loop-timing enable) CKMODE High SMOD[1:0] default = 01 (no effect) Receive Monitor Mode Enable: 0: Normal Operation 1: Adds 20dB of flat gain to the receive signal before equalization NOTE: Monitor mode is only available in CMI mode. Reserved 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 13
... This reset should be initiated anytime the transmitter or IC powers up to ensure the FIFO is centered after internal VCO clocks and external transmit clocks are stable. *Not required for Plesiochronous Serial Mode 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 14
... Optical fiber (LVPECL, NRZ). CMI ENDEC and line driver are disabled. Use RXxP/N and ECLxP/N pins for line interface. 1: Coaxial cable (CMI encoded). CMI ENDEC enabled. Optical (NRZ) interface disabled. Use RXxP/N and CMIxP/N pins for line interface. Reserved. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 15
... This bit is set whenever the internal FERR signal is asserted, indicating that the FIFO is operating at its depth limit reset to 0 when the FRST pin is asserted. 0: Normal operation 1: Transmit FIFO phase error DESCRIPTION Reserved for test. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 16
... Used for diagnostics or far end re-timing. Active during reset. Transmit (Serial Mode) LVPECL Data Output: Transmit NRZ data outputs used for interfacing with optical transceiver modules when in Fiber (NRZ) mode. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 17
... Rx DLL and output a steady clock. Receiver CMI or LVPECL Input: The input is either transformer-coupled to coaxial cable for CMI data or AC- coupled at LVPECL levels to an optical transceiver module for NRZ data. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 18
... Note: The default interrupt condition is a loss of lock in the transmitter CDR. Receiver Fault Interrupt Flag (active low): Reserved for future use. Power-On Reset (active low): See Power-On Reset description on use of this pin. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 19
... TRANSMITTER OPERATION section for more information. In PARALLEL mode (SDI_PAR high): • Low: Parallel transmit clock is input to the 78P2352. • Float: Parallel transmit clock is input to the 78P2352. Loop-timing mode enabled. • High: Parallel transmit clock is output from the 78P2352 In SERIAL mode (SDI_PAR low): • ...
Page 20
... Selects the reference frequency that is supplied at the CKREFP/N pins. Its level is read in only at power- the rising edge of a reset signal at the PORB pin. • Low: 19.44MHz or 17.408MHz • Float: 77.76MHz • High: 155.52MHz or 139.264MHz 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 21
... Selects E4 operation (input high) or STM1/STS3 operation (input low) TYPE DESCRIPTION S Power Supply S CMOS I/O Driver Supply G Ground G CMOS I/O Driver Ground Trim Ground G Used during production test. Connect directly to ground. Do not decouple to supply or PORB. 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...
Page 22
... Fiber (NRZ) mode Transmitter disabled; STM-1 mode; Iddr CMI mode; Max. cable length STM-1 mode; CMI mode; Iddx Max. cable length Iddq PDTX = 1, PDRX = 1 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX UNIT 325 mA 350 290 310 mA 190 ...
Page 23
... Vih Iil, Iih Rpu Type CIU only Rpd Type CID only Cin SYMBOL CONDITIONS Vtil Vtih Rtiz SYMBOL CONDITIONS Vt+ Vt- Iil, Iih Cin 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX 1.9 2.1 2 MIN NOM MAX 0.8 0.4 2 ...
Page 24
... Vdd referenced Reff Tr 10-90% Tf 10-90% SYMBOL CONDITIONS Vpki Vcm Vdd referenced SYMBOL CONDITIONS Vol Iol = 8mA Ipd Logic high output Rpu 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX UNIT 0.4 2 µ MIN NOM MAX UNIT 0.5 ...
Page 25
... SCK t prop PA0 PA1 PA2 PA3 D0 D1 Figure 9: Read Operation PA0 PA1 PA2 PA3 Figure 10: Write Operation 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN TYP MAX ...
Page 26
... SYMBOL CONDITIONS TTCF/TTC PTOxCK TPS Parallel mode TPH Parallel mode TSS Serial mode TSH Serial mode TSS TPS TRC = 25.72ns TPS 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX UNIT TSH ...
Page 27
... Synchronous mode; STM1 -- Plesiochronous or Loop-timing mode. (see Note 1) CONDITIONS RSCQ Serial mode RPCQ Parallel mode TRC = 6.43ns TRCT RSCQ TRC = 25.72ns RPCQ 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX UNIT -15 +15 -20 +20 ppm -75 +75 ...
Page 28
... Page (continued) CONDITION Template, steady state 10-90% Negative Transitions Positive Transitions at Interval Boundaries Positive Transitions at mid- interval With respect to CKREF CONDITION Driver is open drain 7MHz to 240MHz 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN NOM MAX UNIT 0.9 1.05 1 -0.1 0.1 -0.5 ...
Page 29
... Figure 11 – Mask of a Pulse corresponding to a binary Zero in E4 mode Page (continued 7.18ns 1.795 ns 1ns 0.1ns 0.35ns 0.35ns 1ns 1ns 1.795 ns 1.795 ns (Note 1) 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU (Note 1) Nominal Pulse 1.795 ns 1ns 0.1ns 0.1ns 1ns (Note 1) Rev. 2.4 ...
Page 30
... Figure 12 – Mask of a Pulse corresponding to a binary One in E4 mode. Page (continued 7.18ns 0.1ns 3.59ns 1.35ns 1.35ns 1ns 1.795 ns (Note 1) 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU (Note 1) 1ns 0.5ns 0.5ns Nominal Pulse 3.59ns 1ns 1.795 ns Rev. 2.4 ...
Page 31
... Figure 13 – Mask of a Pulse corresponding to a binary Zero in STS-3/STM-1 mode. Page (continued 6.43ns 1.608ns 1ns 0.1ns 0.35ns 0.35ns 1ns 1ns 1.608ns 1.608ns (Note 1) 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU (Note 1) Nominal Pulse 1.608ns 1ns 0.1ns 0.1ns 1ns (Note 1) Rev. 2.4 ...
Page 32
... Figure 14 – Mask of a Pulse corresponding to a binary One in STS-3/STM-1 mode Page (continued) 6.43ns 0.1ns 3.215ns 1.2ns 1.2ns 1ns 1.608ns (Note 1) 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU (Note 1) 1ns 0.5ns 0.5ns Nominal Pulse 3.215ns 1ns 1.608ns Rev. 2.4 ...
Page 33
... CONDITION CMI Mode; 200 Hz to 3.5 MHz, measured with respect to CKREF for 60s NRZ (optical) Mode; 12 kHz to 1.3 MHz, measured with respect to CKREF 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Measured Jitter Amplitude MIN NOM MAX UNIT 0.075 UIpp ...
Page 34
... CMI mode; MON=0; All valid cable lengths. STM-1 mode; CMI mode; 12.7 dB cable loss a) Normal receive mode b) Remote loopback mode 7MHz to 240MHz 1.00E+06 1.00E+07 Frequency (Hz) Worst Case Typical 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU MIN TYP MAX 70 550 0.1 0.07 ...
Page 35
... ELECTRICAL SPECIFICATIONS RECEIVER JITTER TOLERANCE The 78P2352 exceeds all relevant jitter tolerance specifications shown in Figures 16, 17. STS-3/OC-3 jitter tolerance specifications are in ANSI T1.105.03-1994 and Telcordia GR-253-CORE. tolerance specifications are in ITU-T G.813, G.825, and G.958. specifications are in ITU-T G.825. E4 specifications are found in ITU-T G.823. Receive jitter tolerance is not tested during production test ...
Page 36
... Jitter Frequency CONDITION 10Hz to 19.3Hz 19.3Hz to 68.7Hz 68.7Hz to 6.5kHz 6.5kHz to 65kHz 65kHz to 1.3MHz 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Optical (NRZ) Interfaces G.813, G.958, T1.105.03, GR-253 STM-1 / STS-3 / OC-3 Tolerance G.825 - STM-1 Tolerance 100kHz 1MHz 10MHz MIN ...
Page 37
... PARAMETER Receiver Jitter transfer function Jitter transfer function roll-off Page (continued) 1.00E+04 1.00E+05 Figure 18: Jitter Transfer CONDITION below 120 kHz 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU 1.00E+06 1.00E+07 MIN NOM MAX UNIT 0 per 20 decade ...
Page 38
... PACKAGE Standard 128-pin JEDEC LQFP (78P2352- (Recommended) Thernally enhanced Exposed Pad 128-pin JEDEC LQFP (78P2352- SCHEMATICS For reference schematics, layout guidelines, recommended transformer part numbers, etc. please check Teridian Semiconductor's website or contact your local sales representative for the latest application note(s) and/or demo board manuals ...
Page 39
... Page 16.000 +/- 0.200 14.000 +/- 0.100 12.400 REF. MAX. 1.600 1.400 +/- 0.050 0.400 IEL 78P2352- 128-pin Exposed Pad JEDEC LQFP (Bottom View) 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU 128 1 0.100 +/- 0.050 0.600 +/- 0.150 Rev. 2.4 ...
Page 40
... MECHANICAL SPECIFICATIONS 0.40 Typ. (0.015) 0.60 Typ. (0.024) 128-pin Standard JEDEC LQFP ( Page 15.8 (0.622) 16.2 (0.637) Top View 13.8 (0.543) 14.2 (0.559) . 1.60 Max (0.063) 0.13 (0.005) 0.23 (0.009) Side View IGT 78P2352- Top View 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU 0.05 (0.002) 0.15 (0.006) ) Rev. 2.4 ...
Page 41
... SDI_PAR 94 SDO_E4 93 VCC 92 GND 91 SI2CKP 90 SI2CKN 89 INTTX1B 88 SI2DP 87 SI2DN 86 VCC 85 GND 84 PORB 83 TGND 82 CKSL 81 80 LOS1 LOL1 79 FRST 78 SPSL 77 N/C 76 N/C 75 VCC 74 GND 73 SO2CKP 72 SO2CKN 71 INTRX1B 70 SO2DP 69 SO2DN 68 PI2CK 67 PI20D 66 PI21D 65 PACKAGE MARK 78P2352-IGT xxxxxxxxxxP6 70P2352-IGT xxxxxxxxxxP6 78P2352-IEL xxxxxxxxxxP6 n/a xxxxxxx-xxx xxxxxxxxxxP6F Rev. 2.4 ...
Page 42
... TSC assumes no liability for applications assistance. Teridian Semiconductor Corp., 6440 Oak Canyon, Irvine, CA 92618 TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridiansemiconductor.com Page Revison History 2006 Teridian Semiconductor Corporation 78P2352 Dual Channel OC-3/ STM1-E/ E4 LIU Rev. 2.4 ...