78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 16

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

LEGEND
TYPE
TRANSMITTER PINS
NAME
PIx0D
PIx1D
PIx2D
PIx3D
PIxCK
PTOxCK
SIxDP
SIxDN
SIxCKP
SIxCKN
CMIxP
CMIxN
TXxCKP
TXxCKN
ECLxP
ECLxN
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CIU
CID
CIT
CIS
PIN DESCRIPTION
CI
PI
A
DESCRIPTION
Analog Pin
(Tie unused pins to ground)
3-State CMOS Digital Input
CMOS Digital Input
(Tie unused pins to ground)
CMOS Digital Input w/ Pull-up
CMOS Digital Input w/ Pull-down
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
121, 104
122, 103
124, 101
125, 100
127, 98
128, 97
31, 66
32, 65
33, 64
34, 63
30, 67
35, 62
10, 87
11, 86
7, 90
8, 89
PIN
TYPE
CIS
CO
PO
PO
CI
PI
PI
A
DESCRIPTION
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
Transmit (Serial Mode) Data Input:
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
Transmit (Serial Mode) Clock Input:
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SIxCKP.
Transmit (Serial Mode) CMI Data Output:
A CMI encoded data signal conforming to the relevant ITU-T G.703 pulse
templates when properly terminated and transformer coupled to 75Ω cable.
Outputs are tri-stated when transmitter is disabled. Active, but undefined
during reset.
Transmit (Serial Mode) Clock Output:
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
Transmit (Serial Mode) LVPECL Data Output:
Transmit NRZ data outputs used for interfacing with optical transceiver
modules when in Fiber (NRZ) mode.

2006 Teridian Semiconductor Corporation
TYPE
COZ
CO
OD
PO
G
S
DESCRIPTION
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CMOS Digital Output
(Leave unused pins floating)
CMOS Tristate Digital Output
(Leave unused pins floating)
Open-drain Digital Output
(Leave unused pins floating)
Supply
Ground
OC-3/ STM1-E/ E4 LIU
Dual Channel
78P2352
Rev. 2.4