78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 18

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

REFERENCE AND STATUS PINS
Note: The LOSx, LOLx, and INTxXxB pins are configurable at final test (default open-drain outputs). If CMOS
level outputs are required, please refer to alternate 70Pxxxx ordering numbers at the end of the data sheet.
NAME
CKREFP
CKREFN
LOS1
LOS2
LOL1
LOL2
INTTX1B
INTTX2B
INTRX1B
INTRX2B
PORB
Page: 18 of 42
PIN DESCRIPTION
PIN
111
110
80
19
79
20
88
70
27
83
9
TYPE
(CONTINUED)
OD/
OD/
OD/
OD/
CO
CO
CO
CO
PI/
CI
A
DESCRIPTION
Reference Clock Input:
A required reference clock input used for clock/data recovery and frequency
synthesizer. Options include :
Receive Loss of Signal (active-high):
See Receiver Loss of Signal description for conditions.
Receive Loss of Lock (active-high):
This condition is met when the recovered clock frequency differs from the
reference clock frequency by more than +/- 100ppm.
Transmitter Fault Interrupt Flag (active low):
When a transmitter error event occurs (as defined in the Interrupt Control
Register Description), the INTTXxB pin will change state to indicate an
interrupt. The interrupt is cleared by a read to the STAT Register, an issue
of a FRSTx FIFO reset pulse (if the FIERRx signal caused the interrupt), or
when the TXLOL register bit transitions from high to low.
Note: The default interrupt condition is a loss of lock in the transmitter CDR.
Receiver Fault Interrupt Flag (active low):
Reserved for future use.
Power-On Reset (active low):
See Power-On Reset description on use of this pin.
• 139.264 MHz (E4) or 155.52 MHz (STM1) differential LVPECL clock
• 17.408 MHz (E4), 19.44 MHz (STM1), or 77.78 MHz (STM1) single-

input at CKREFP/N
ended CMOS clock input at CKREFP. Tie CKREFN to ground when
unused.
2006 Teridian Semiconductor Corporation
OC-3/ STM1-E/ E4 LIU
Dual Channel
78P2352
Rev. 2.4