78P2352-IEL TERIDIAN [Teridian Semiconductor Corporation], 78P2352-IEL Datasheet - Page 12

• Manufacturer Part Number: 78P2352-IEL
• Description: Dual Channel OC-3/ STM1-E/ E4 LIU
• Manufacturer: TERIDIAN [Teridian Semiconductor Corporation]

REGISTER DESCRIPTION
PORT-SPECIFIC REGISTERS
For PA[3:0] = 1-2 = N only. Accessing a register with port address greater than 2 constitutes an invalid command,
and the read/write operation will be ignored.
ADDRESS N-0: MODE CONTROL REGISTER
Page: 12 of 42
BIT
1:0
7
6
5
4
3
2
SMOD[1]
SMOD[0]
PMODE
NAME
PDRX
PDTX
MON
--
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
VALUE
DFLT
00
X
X
X
0
0
0
(CONTINUED)
DESCRIPTION
Transmitter Power-Down:
Receiver Power-Down:
Parallel Mode Interface Selection:
Serial Mode Interface Selection:
Receive Monitor Mode Enable:
NOTE: Monitor mode is only available in CMI mode.
Reserved

When PAR=0, PMODE is invalid and defaults to logic ‘1’;
When PAR=1, (Master Control Register: bit 5), PMODE selects the
source of the transmit parallel clock, either taken from the framer
externally or generated internally. Default value is determined by
CKMODE pin setting upon power up or reset.
When PAR=0 (Master Control Register: bit 5), SMOD[1:0] configures
the transmitter’s system interface. Default values determined by
CKMODE pin setting upon power up or reset.
SMOD[1] SMOD[0]
When PAR=1 (Master Control Regsiter: bit 5), setting SMOD[1:0] = 11
will enable Loop Timing Mode. Default values are determined by
CKMODE pin setting upon power up or reset as follows:
2006 Teridian Semiconductor Corporation
0
1
0
1
0 : Normal Operation
1 : Power-Down. CMI Transmit output is tri-stated.
0 : Normal Operation
1 : Power-Down
0: Normal Operation
1: Adds 20dB of flat gain to the receive signal before equalization
1: Master Timing. PTOxCK clock output from the transmitter
0: Slave Timing. PIxCK clock input to the transmitter
CKMODE Low
CKMODE Float
CKMODE High
0
0
1
1
Synchronous clock and data are passed through a
FIFO. The CDR is bypassed.
Synchronous data is passed through the CDR and
then through the FIFO.
Plesiochronous data is passed through the CDR to
recover a clock. FIFO is bypassed because the
data is not synchronous with the reference clock.
Loop Timing Mode Enable: The recovered receive
clock is used as the reference for the transmit DLL
and FIFO.
SMOD[1:0] default = 00 (no effect)
SMOD[1:0] default = 11 (loop-timing enable)
SMOD[1:0] default = 01 (no effect)
OC-3/ STM1-E/ E4 LIU
Dual Channel
78P2352
Rev. 2.4