Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 66
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Z8F082A28100KIT
Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8F082A28100KIT.pdf
(244 pages)
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Architecture
Operation
PS024705-0405
Priority
Lowest
Master Interrupt Enable
Program Memory
Vector Address
0036H
0038H
Figure 7 illustrates the interrupt controller block diagram.
The master interrupt enable bit (IRQE) in the Interrupt Control register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
•
Internal Interrupts
Table 31. Trap and Interrupt Vectors in Order of Priority (Continued)
Port Interrupts
Execution of an EI (Enable Interrupt) instruction
Execution of an IRET (Return from Interrupt) instruction
Interrupt or Trap Source
Port C0, both input edges
Reserved
Figure 7.Interrupt Controller Block Diagram
P R E L I M I N A R Y
Medium
Priority
Priority
Priority
High
Low
Priority
Z8 Encore! XP
Mux
Product Specification
Vector
IRQ Request
®
Interrupt Controller
F08xA Series
48
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