Z8F082A28100KIT ZILOG [Zilog, Inc.], Z8F082A28100KIT Datasheet - Page 41
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Z8F082A28100KIT
Manufacturer Part Number
Z8F082A28100KIT
Description
Z8 Encore XP-R F08xA Series with eXtended Peripherals
Manufacturer
ZILOG [Zilog, Inc.]
Datasheet
1.Z8F082A28100KIT.pdf
(244 pages)
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PS024705-0405
Internal RESET
System Clock
Note: Not to Scale
WDT Clock
VCC = 3.3V
signal
Watch-Dog Timer Reset
External Reset Input
V
V
POR
VBO
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a power on reset after recovering from a VBO condition.
If the device is in NORMAL or STOP mode, the Watch-Dog Timer can initiate a System
Reset at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the
unprogrammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it
configures the Watch-Dog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control register is set to signify that the reset was initi-
ated by the Watch-Dog Timer.
The RESET pin has a Schmitt-triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of 4 system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
clock and reset signals, the required reset duration may be as short as three clock periods
Execution
Program
Figure 5.Voltage Brown-Out Reset Operation
Brownout
Voltage
P R E L I M I N A R Y
counter delay
POR
Z8 Encore! XP
Reset and STOP Mode Recovery
Product Specification
Execution
Program
®
F08xA Series
VCC = 3.3V
23
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