HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet - Page 49

• Manufacturer Part Number: HYB18T512160AF-3
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
5) Inputs are not recognized as valid until
6) The output timing reference voltage level is
7) For each of the terms, if not already an integer, round to the next highest integer.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
9) For timing definition, refer to the Component data sheet.
10) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
11) MIN (
12) The
13) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
14) 0 °C≤
15) 85 °C <
16) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
17) The t
18) The maximum limit for the
19) Minimum
20) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
21) WR must be programmed to fulfill the minimum requirement for the
Rev. 1.71, 2007-01
03062006-CPCN-4867
Parameter
Exit Self-Refresh to Read command
Write recovery time for write with Auto-
Precharge
V
and then restarted through the specified initialization sequence before normal operation can continue.
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
input reference level is the crosspoint when in differential strobe mode.
the WR parameter stored in the MR.
mis-match between DQS / DQS and associated DQ in any given cycle.
be greater than the minimum specification limits for
(
parameters are verified by design and characterization, but not subject to production test.
and 95 °C.
products” on Page
performance (bus turnaround) degrades accordingly.
down mode” (MR, A12 = “0”) a fast power-down exit timing
power-down exit timing
up to the next integer value.
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
t
HZ,
DDQ
t
t
RRD
HZ
RPST
t
= 1.8 V ± 0.1 V;
CL
T
,
CASE
,
T
t
timing parameter depends on the page size of the DRAM organization. See
RPST
), or begins driving (
t
CASE
t
CH
WTR
) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
≤ 85 °C
and
≤ 95 °C
is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
t
LZ
,
6.
t
V
RPRE
DD
t
XARDS
= 1.8 V ±0.1 V. See notes
t
parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
WPST
t
t
DAL
LZ,
has to be satisfied.
t
parameter is not a device limit. The device operates with a greater value for this parameter, but system
= WR + (
RPRE
).
V
t
HZ
REF
t
RP
and
V
stabilizes. During the period before
/
TT
t
CK
.
t
LZ
). For each of the terms, if not already an integer, round to the next highest integer.
transitions occur in the same access time windows as valid data transitions.These
Symbol
t
WR
XSRD
t
CL
4)5)6)7)
and
t
t
CH
XARD
).
49
can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
t
WR
DDR2–400
200
t
Min.
WR
timing parameter, where
/
t
CK
V
t
REF
CK
Table 5 “Ordering Information for RoHS compliant
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
refers to the application clock period. WR refers to
stabilizes, CKE = 0.2 x
Max.
—
—
WR
MIN
[cycles] =
512-Mbit DDR2 SDRAM
V
DDQ
Unit
t
t
Internet Data Sheet
CK
CK
t
WR
is recognized as low.
(ns)/
t
Note
6)
—
21)
CK
(ns) rounded
1)2)3)4)5)
t
CK