HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet - Page 33

• Manufacturer Part Number: HYB18T512160AF-3
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) Absolute Specifications (
2)
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and represents only the
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured from AC to AC.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MHz speed bins.
5.5
This chapter describes the Input / Output Capacitance.
Rev. 1.71, 2007-01
03062006-CPCN-4867
Symbol
—
—
—
S
Symbol
CCK
CDCK
CI
CDI
CIO
CDIO
OUT
meet timing, voltage and slew rate specifications on I/O’s.
23.4 ohms for values of
V;
DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
conditions.
This is verified by design and characterization but not subject to production test.
specification.
Impedance measurement condition for output source dc current:
V
OUT
= –280 mV;
Parameter
Input capacitance, CK and CK
Input capacitance delta, CK and CK
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance,
DQ, DM, DQS, DQS, RDQS, RDQS
Input/output capacitance delta,
Description
Output Impedance
Pull-up / Pull down mismatch
Output Impedance step size
for OCD calibration
Output Slew Rate
DQ, DM, DQS, DQS, RDQS, RDQS
Input / Output Capacitance
V
OUT
V
T
OUT
/
OPER
I
OL
between
;
must be less than 23.4 Ohms for values of
V
DD
= 1.8 V
V
DDQ
and
±
0.1 V;
V
DDQ
V
– 280 mV. Impedance measurement condition for output sink dc current:
DDQ = 1.8 V
Min.
—
0
0
1.5
33
V
DDQ
±
0.1 V), altering OCD from default state no longer requires DRAM to
= 1.7 V,
V
OUT
DDR2-400 & DDR-
2-533
Min.
1.0
—
—
2.5
—
1.0
Nominal
—
—
—
between 0 V and 280 mV.
V
OUT
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
= 1420 mV; (
Max.
2.0
0.25
2.0
0.25
4.0
0.5
Max.
4
1.5
5.0
OCD Default Characteristics
V
OUT
Input / Output Capacitance
DDR2-667
Min.
1.0
—
1.0
—
2.5
—
±
–
0.75 Ohms under nominal
V
DDQ
512-Mbit DDR2 SDRAM
) /
Unit
Ohms
Ohms
Ohms
V / ns
I
Internet Data Sheet
Max.
2.0
0.25
2.0
0.25
3.5
0.5
OH
t
DQSQ
must be less than
TABLE 31
TABLE 32
and
t
QHS
Note
1)2)
1)2)3)
4)
1)5)6)7)
pF
Unit
pF
pF
pF
pF
pF
V
DDQ
= 1.7