HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet - Page 36

• Manufacturer Part Number: HYB18T512160AF-3
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

6
This chapter contains the currents, specifications and conditions.
Rev. 1.71, 2007-01
03062006-CPCN-4867
Parameter
Operating Current - One bank Active - Precharge
t
and control inputs are switching; Databus inputs are switching.
Operating Current - One bank Active - Read - Precharge
I
CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are switching; Databus
inputs are switching.
Precharge Power-Down Current
All banks idle; CKE is LOW;
floating
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are switching
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
bus inputs are floating.
Active Power-Down Current
All banks open;
are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
All banks open;
are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
All banks open;
commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
switching; Data Bus inputs are switching;
Operating Current
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
switching; Data Bus inputs are switching;
Burst Refresh Current
t
commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
t
commands, Other control and address inputs are switching, Data bus inputs are switching.
CK
OUT
RAS.MAX.(IDD)
RAS.MAX(IDD)
CK
CK
=
=
=
= 0 mA, BL = 4,
t
t
t
CK(IDD)
CK(IDD)
CK(IDD)
.
,
,
,
, Refresh command every
, Refresh command every
t
t
t
RP
RC
RP
t
t
t
=
=
=
CK
CK
CK
t
t
t
RC(IDD)
RP(IDD)
RP(IDD)
=
=
=
Currents, Specifications,Conditions
t
t
t
t
CK
CK(IDD)
CK(IDD)
CK(IDD)
,
=
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
t
RAS
t
CK(IDD)
t
, CKE is LOW; Other control and address inputs are stable; Data bus inputs
, CKE is LOW; Other control and address inputs are stable, Data bus inputs
;
CK
t
.
=
RAS
=
t
RAS.MIN(IDD)
,
t
=
CK(IDD)
t
RC
t
RAS.MAX(IDD)
=
t
t
REFI
RFC
t
; Other control and address inputs are stable; Data bus inputs are
RC(IDD)
I
t
t
, CKE is HIGH, CS is HIGH between valid commands. Address
CK
OUT
CK
=
= 7.8 µs interval, CKE is LOW and CS is HIGH between valid
t
=
=
RFC(IDD)
,
= 0 mA.
,
t
t
t
CK(IDD)
CK(IDD)
RAS
t
RP
=
=
interval, CKE is HIGH, CS is HIGH between valid
; Other control and address inputs are stable, Data
t
; Other control and address inputs are switching,
t
RP(IDD)
RAS.MIN(IDD)
; CKE is HIGH, CS is HIGH between valid
36
,
t
RCD
=
t
RCD(IDD)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
(IDD)
(IDD)
, AL = 0, CL = CL(IDD);
;
;
t
t
CK
CK
=
=
t
t
CK(IDD)
CK(IDD)
I
DD
Measurement Conditions
;
;
t
t
RAS
RAS
512-Mbit DDR2 SDRAM
=
=
Internet Data Sheet
Symbol Note
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TABLE 35
DD0
DD1
DD2P
DD2N
DD2Q
DD3P(0)
DD3P(1)
DD3N
DD4R
DD4W
DD5B
DD5D
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