HYB18T512160AF-3 QIMONDA [Qimonda AG], HYB18T512160AF-3 Datasheet - Page 37

• Manufacturer Part Number: HYB18T512160AF-3
• Description: 512-Mbit Double-Data-Rate-Two SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1)
2)
3)
4) Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
5) Definitions for
6) Timing parameter minimum and maximum values for
7) A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Rev. 1.71, 2007-01
03062006-CPCN-4867
Parameter
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating, Data bus
inputs are floating.
Operating Bank Interleave Read Current
1. All banks interleaving reads,
2. Timing pattern:
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
Parameter
LOW
HIGH
STABLE
FLOATING
SWITCHING
V
I
I
t
are stable during deselects; Data bus is switching.
DD
DD
RC
DDQ
specifications are tested after the device is properly initialized.
parameter are specified with ODT disabled.
=
= 1.8 V ± 0.1 V;
t
RC(IDD)
,
I
DD
t
RRD
Description
defined as
defined as
defined as inputs are stable at a HIGH or LOW level
defined as inputs are
defined as: Inputs are changing between high and low every other clock (once per two clocks) for address
and control signals, and inputs changing between high and low every other clock (once per clock) for DQ
signals not including mask or strobes
: see
=
V
t
Table 36
DD
RRD(IDD)
= 1.8 V ± 0.1 V
V
V
IN
IN
; CKE is HIGH, CS is HIGH between valid commands. Address bus inputs
I
≤
≥
OUT
V
V
IL(ac).MAX
IH(ac).MIN
= 0 mA; BL = 4, CL = CL
V
REF
=
V
DDQ
I
DD
/ 2
current measurements are defined in chapter 7..
37
(IDD)
, AL =
t
RCD(IDD)
HYB18T512[40/80/16]0AF(L)–[3/3S/3.7/5]
-1 ×
t
CK(IDD)
;
t
CK
=
t
512-Mbit DDR2 SDRAM
CK(IDD)
Internet Data Sheet
,
Definition for I
Symbol Note
I
I
TABLE 36
DD6
DD7
1)2)3)4)5)
6)
1)2)3)4)5)
6)7)
DD